Re: [Xen-devel] [PATCH] xen/arm: Set up Versatile Express timer frequency to 24 Mhz

[Stefano Stabellini <stefano.stabellini@xxxxxxxxxxxxx>]

On Mon, 24 Jun 2013, Julien Grall wrote:
> On 06/24/2013 03:52 PM, Stefano Stabellini wrote:
> 
> > On Mon, 24 Jun 2013, Tim Deegan wrote:
> >> At 14:10 +0100 on 24 Jun (1372083058), Julien Grall wrote:
> >>> On TC2, the timer frequency was set to 100 Mhz which slows down the whole
> >>> platform.
> >>> When Linux is running on bare metal, the frequency is 24 Mhz.
> >>>
> >>> "sleep 60" in dom0 takes:
> >>>   - 4 mins with a frequency equals to 100 Mhz
> >>>   - 1 min with a frequency equals to 24 Mhz
> >>>
> >>> Signed-off-by: Julien Grall <julien.grall@xxxxxxxxxx>
> >>
> >> Is this a problem with the vexpress (e.g. the timer runs at 24MHz
> >> regardless of this setting, which would explain the otherwise odd
> >> numbers you give above), or just that linux code assumes the timer is
> >> always 24MHz?
> >>
> >> If it's the latter, I think it needs to be fixed on the linux side.  Xen
> >> can't let the guest OS dictate things like this, since we might want to
> >> run two guests with different OSes.  Also, if linux changes its choice,
> >> we'd have trouble with old and new linux running together.
> > 
> > Linux gets the frequency from:
> > 
> > 1) device tree
> > 2) the arch timer register
> > 
> > in this order.
> > Either way it should work.
> > 
> > Could it be that Xen is failing to set the frequency on the versatile
> > express? Therefore the hardware is running the timer at a different
> > frequency than Xen is expecting it to?
> 
> 
> 
> Lots of place in the DTS and the board configuration use a frequency of
> 24Mhz.
> On the arndale, the timer frequency is 24Mhz, why do we need 100Mhz on
> the versatile express?
> 
> It seems U-boot uses SP810 to modify the clock frequency on the
> versatile express but I can't find documentation about the different
> registers.

In that case, if Xen is actually unable of changing the clock frequency,
just go ahead and remove:

        /* Ugly: the system timer's frequency register is only
         * programmable in Secure state.  Since we don't know where its
         * memory-mapped control registers live, we can't find out the
         * right frequency. */
        mcr   CP32(r0, CNTFRQ)

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