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[Date Prev][Date Next][Thread Prev][Thread Next][Date Index][Thread Index] Re: [Xen-devel] [PATCH 1/2 v5] iommu/amd: Fix logic for clearing the IOMMU interrupt bits
On 6/11/2013 1:47 AM, Jan Beulich wrote: If more entries are added to the event log during the time that event log interrupt is disabled (in the control register), the IOMMU hardware will generate interrupt once the the interrupt enable bit in the control register changes from 0 to 1 and set the status register. Since the "iommu_interrupt_handler" code is already calling "schedule_tasklet", we should not need to "re-schedule" tasklet here. I have confirmed the hardware behavior described with the hardware designer. This is also the same on the PPR log. Suravee _______________________________________________ Xen-devel mailing list Xen-devel@xxxxxxxxxxxxx http://lists.xen.org/xen-devel
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