[Date Prev][Date Next][Thread Prev][Thread Next][Date Index][Thread Index] Re: [Xen-devel] CAP and performance problem
Hi dario, Sort of. However, since (you said) you have 4 cores, what I was thinking was more a situation where you have the 4 Dom0 vCPUs pinned to cores 0-2, and the VM vCPU pinned to core 3. You should be able to achieve that by doing right this: # xl vcpu-pin 0 all 0-2 # xl vcpu-pin rubis-web all 3 I have set pin as you suggested: [root@csitest ~]# xl vcpu-pin 0 all 0-2 [root@csitest ~]# xl vcpu-pin rubis-web all 3 [root@csitest ~]# xl vcpu-listName ID VCPU CPU State Time(s) CPU Affinity Domain-0 0 0 0 -b- 384.5 0-2 Domain-0 0 1 2 -b- 358.9 0-2 Domain-0 0 2 2 -b- 224.6 0-2 Domain-0 0 3 1 r-- 257.0 0-2 rubis-web 1 0 3 -b- 9251.6 3 No hyperthreading are involved. At the end of this email I've pasted what /proc/cpuinfo says about cores (they are actual cores).Does it make sense? Oh, and also, you have 4 _actual_cores_, right? Or is there any hyperthreading involved? The experiment just finished said again that the service time is 3 times longer when CAP=50% with respect to the scenario with CAP=100%. If you want me do more experiment, just let me know, I'll be happy to collaborate. I can also provide you my code: it's a very simple C++ code with a makefile that make you ready to run it in few seconds. Cheers, Massimo [root@csitest ~]# cat /proc/cpuinfo processor : 0 vendor_id : GenuineIntel cpu family : 6 model : 15 model name : Intel(R) Xeon(R) CPU 5160 @ 3.00GHz stepping : 6 microcode : 0xd2 cpu MHz : 3000.186 cache size : 4096 KB fpu : yes fpu_exception : yes cpuid level : 10 wp : yesflags : fpu de tsc msr pae mce cx8 apic sep mca cmov pat clflush acpi mmx fxsr sse sse2 ss ht syscall nx lm constant_tsc rep_good nopl pni monitor est ssse3 cx16 hypervisor lahf_lm dtherm bogomips : 6000.37 clflush size : 64 cache_alignment : 64 address sizes : 36 bits physical, 48 bits virtual power management: processor : 1 vendor_id : GenuineIntel cpu family : 6 model : 15 model name : Intel(R) Xeon(R) CPU 5160 @ 3.00GHz stepping : 6 microcode : 0xd2 cpu MHz : 3000.186 cache size : 4096 KB fpu : yes fpu_exception : yes cpuid level : 10 wp : yesflags : fpu de tsc msr pae mce cx8 apic sep mca cmov pat clflush acpi mmx fxsr sse sse2 ss ht syscall nx lm constant_tsc rep_good nopl pni monitor est ssse3 cx16 hypervisor lahf_lm dtherm bogomips : 6000.37 clflush size : 64 cache_alignment : 64 address sizes : 36 bits physical, 48 bits virtual power management: processor : 2 vendor_id : GenuineIntel cpu family : 6 model : 15 model name : Intel(R) Xeon(R) CPU 5160 @ 3.00GHz stepping : 6 microcode : 0xd2 cpu MHz : 3000.186 cache size : 4096 KB fpu : yes fpu_exception : yes cpuid level : 10 wp : yesflags : fpu de tsc msr pae mce cx8 apic sep mca cmov pat clflush acpi mmx fxsr sse sse2 ss ht syscall nx lm constant_tsc rep_good nopl pni monitor est ssse3 cx16 hypervisor lahf_lm dtherm bogomips : 6000.37 clflush size : 64 cache_alignment : 64 address sizes : 36 bits physical, 48 bits virtual power management: processor : 3 vendor_id : GenuineIntel cpu family : 6 model : 15 model name : Intel(R) Xeon(R) CPU 5160 @ 3.00GHz stepping : 6 microcode : 0xd2 cpu MHz : 3000.186 cache size : 4096 KB fpu : yes fpu_exception : yes cpuid level : 10 wp : yesflags : fpu de tsc msr pae mce cx8 apic sep mca cmov pat clflush acpi mmx fxsr sse sse2 ss ht syscall nx lm constant_tsc rep_good nopl pni monitor est ssse3 cx16 hypervisor lahf_lm dtherm bogomips : 6000.37 clflush size : 64 cache_alignment : 64 address sizes : 36 bits physical, 48 bits virtual power management: _______________________________________________ Xen-devel mailing list Xen-devel@xxxxxxxxxxxxx http://lists.xen.org/xen-devel
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