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Re: [Xen-devel] Some trouble to use NVIDIA CUDA with Xen



This is the part we are interested in:

Sébastien Frémal, le Tue 30 Apr 2013 16:32:45 +0200, a écrit :
> 648c648
> < Latency: 0, Cache Line Size: 64 bytes
> ---
> > Latency: 0
> 654c654
> < Expansion ROM at f7e00000 [disabled] [size=512K]
> ---
> > [virtual] Expansion ROM at f7e00000 [disabled] [size=512K]
> 660,661c660,661
> < Capabilities: [78] Express (v1) Endpoint, MSI 00
> < DevCap: MaxPayload 128 bytes, PhantFunc 0, Latency L0s <1us, L1 <4us
> ---
> > Capabilities: [78] Express (v2) Endpoint, MSI 00

So it seems the whole PCI express negociation changes...

> > DevCap: MaxPayload 128 bytes, PhantFunc 0, Latency L0s <512ns, L1 <4us
> 664c664
> < RlxdOrd+ ExtTag- PhantFunc- AuxPwr- NoSnoop+
> ---
> > RlxdOrd+ ExtTag+ PhantFunc- AuxPwr- NoSnoop+
> 666,667c666,667
> < DevSta: CorrErr+ UncorrErr- FatalErr- UnsuppReq- AuxPwr- TransPend-
> < LnkCap: Port #0, Speed 2.5GT/s, Width x16, ASPM L0s L1, Latency L0 <1us, L1
> <1us
> ---
> > DevSta: CorrErr- UncorrErr- FatalErr- UnsuppReq- AuxPwr- TransPend-
> > LnkCap: Port #0, Speed 5GT/s, Width x16, ASPM L0s L1, Latency L0 <256ns, L1

Resulting in a different speed

> <1us
> 671c671,678
> < LnkSta: Speed 2.5GT/s, Width x16, TrErr- Train- SlotClk- DLActive- BWMgmt- 
> ABWMgmt-
> ---
> > LnkSta: Speed 5GT/s, Width x16, TrErr- Train- SlotClk- DLActive- BWMgmt- 
> > ABWMgmt-
> > DevCap2: Completion Timeout: Not Supported, TimeoutDis+
> > DevCtl2: Completion Timeout: 50us to 50ms, TimeoutDis-
> > LnkCtl2: Target Link Speed: 2.5GT/s, EnterCompliance- SpeedDis-, Selectable 
> > De-emphasis: -6dB
> > Transmit Margin: Normal Operating Range, EnterModifiedCompliance- 
> > ComplianceSOS-
> > Compliance De-emphasis: -6dB
> > LnkSta2: Current De-emphasis Level: -6dB, EqualizationComplete-, 
> > EqualizationPhase1-
> > EqualizationPhase2-, EqualizationPhase3-, LinkEqualizationRequest-

And additional capabilities.

Samuel

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