[Xen-devel] [PATCH 1 of 2] x86/x2apic: Sandy-Bridge BT98 Erratum

[Andrew Cooper <andrew.cooper3@xxxxxxxxxx>]

Reference:
http://www.intel.com/content/dam/www/public/us/en/documents/specification-updates/xeon-e5-family-spec-update.pdf

Disable x2apic on affected systems.

This requires exposing apic_boot_mode outside of apic.c

Signed-off-by: Andrew Cooper <andrew.cooper3@xxxxxxxxxx>

diff -r be00287ccdf0 -r 89ba0b0192c4 xen/arch/x86/apic.c
--- a/xen/arch/x86/apic.c
+++ b/xen/arch/x86/apic.c
@@ -78,7 +78,7 @@ boolean_param("x2apic", opt_x2apic);
  * Bootstrap processor local APIC boot mode - so we can undo our changes
  * to the APIC state.
  */
-static enum apic_mode apic_boot_mode = APIC_MODE_INVALID;
+enum apic_mode apic_boot_mode = APIC_MODE_INVALID;
 
 bool_t __read_mostly x2apic_enabled = 0;
 bool_t __read_mostly directed_eoi_enabled = 0;
diff -r be00287ccdf0 -r 89ba0b0192c4 xen/arch/x86/genapic/probe.c
--- a/xen/arch/x86/genapic/probe.c
+++ b/xen/arch/x86/genapic/probe.c
@@ -56,12 +56,51 @@ static void __init genapic_apic_force(ch
 }
 custom_param("apic", genapic_apic_force);
 
+/* Xeon E5 Family processors (Sandy-Bridge) suffer from erratum BT98, which
+ * affects Stepping C-1, but is reported fixed in Stepping C-2.
+ *
+ * This causes system instability when using x2apic and VT-d queued
+ * invalidation.  The workaround is to disable x2apic and VT-d.
+ */
+static void __init smb_bt98_erratum(void)
+{
+       const struct cpuinfo_x86 *c = &boot_cpu_data;
+
+       if (!(c->x86_vendor == X86_VENDOR_INTEL &&
+             c->x86 == 6 &&
+             c->x86_model == 0x2d &&
+             c->x86_mask == 0x6))
+               return;
+
+       printk(KERN_WARNING
+              "Disabling x2apic due to Sandy-Bridge BT98 erratum\n");
+
+       clear_bit(X86_FEATURE_X2APIC, boot_cpu_data.x86_capability);
+       x2apic_enabled = 0;
+
+       /* If the BIOS started us in x2apic mode, switch back to xapic. */
+       if (apic_boot_mode == APIC_MODE_X2APIC) {
+               uint64_t msr;
+
+               rdmsrl(MSR_IA32_APICBASE, msr);
+               msr &= ~(MSR_IA32_APICBASE_ENABLE|MSR_IA32_APICBASE_EXTD);
+               wrmsrl(MSR_IA32_APICBASE, msr);
+               msr |= MSR_IA32_APICBASE_ENABLE;
+               wrmsrl(MSR_IA32_APICBASE, msr);
+
+               apic_boot_mode = APIC_MODE_XAPIC;
+       }
+}
+
 void __init generic_apic_probe(void) 
 { 
        int i, changed;
 
        record_boot_APIC_mode();
 
+        /* Must be before check_x2apic_preenabled() */
+       smb_bt98_erratum();
+
        check_x2apic_preenabled();
        cmdline_apic = changed = (genapic != NULL);
 
diff -r be00287ccdf0 -r 89ba0b0192c4 xen/include/asm-x86/apic.h
--- a/xen/include/asm-x86/apic.h
+++ b/xen/include/asm-x86/apic.h
@@ -28,6 +28,7 @@ enum apic_mode {
     APIC_MODE_XAPIC,    /* xAPIC mode - default upon chipset reset */
     APIC_MODE_X2APIC    /* x2APIC mode - common for large MP machines */
 };
+extern enum apic_mode apic_boot_mode;
 
 extern u8 apic_verbosity;
 extern bool_t x2apic_enabled;

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