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Re: [Xen-devel] [PATCH 1/6] AMD IOMMU: allocate IRTE entries instead of using a static mapping

To: Jan Beulich <JBeulich@xxxxxxxx>
From: Suravee Suthikulanit <suravee.suthikulpanit@xxxxxxx>
Date: Tue, 23 Apr 2013 10:06:54 -0500
Cc: Konrad Rzeszutek Wilk <konrad.wilk@xxxxxxxxxx>, Jacob Shin <jacob.shin@xxxxxxx>, xiantao.zhang@xxxxxxxxx, xen-devel <xen-devel@xxxxxxxxxxxxx>
Delivery-date: Tue, 23 Apr 2013 15:07:23 +0000
List-id: Xen developer discussion <xen-devel.lists.xen.org>

On 4/23/2013 8:21 AM, Suravee Suthikulanit wrote:

I am now reproducing the issue with the USB devices not working withthis patch again. I'll continue to investigate more.
Suravee

Ok, I have more update on the issue. Bellow, I include the output from"xl debug-key i". It is showing several IRQ having the same vector "b0".

This is not the case when booting with the xen w/o the patch.

On my system, IRQ 18 is for my USB keyboard.

Suravee

## INTERRUPT BINDING (i)
(XEN) Guest interrupt information:

(XEN) IRQ: 0 affinity:1 vec:f0 type=IO-APIC-edge status=00000000timer_interrupt+0/0x18a(XEN) IRQ: 1 affinity:1 vec:30 type=IO-APIC-edge status=00000002mapped, unbound(XEN) IRQ: 3 affinity:1 vec:38 type=IO-APIC-edge status=00000002mapped, unbound(XEN) IRQ: 4 affinity:1 vec:40 type=IO-APIC-edge status=00000002mapped, unbound(XEN) IRQ: 5 affinity:f vec:48 type=IO-APIC-edge status=00000002mapped, unbound(XEN) IRQ: 6 affinity:1 vec:50 type=IO-APIC-edge status=00000002mapped, unbound(XEN) IRQ: 7 affinity:1 vec:58 type=IO-APIC-edge status=00000002mapped, unbound(XEN) IRQ: 8 affinity:1 vec:60 type=IO-APIC-edge status=00000010in-flight=0 domain-list=0: 8(----),(XEN) IRQ: 9 affinity:1 vec:68 type=IO-APIC-level status=00000010in-flight=0 domain-list=0: 9(----),(XEN) IRQ: 10 affinity:1 vec:70 type=IO-APIC-edge status=00000002mapped, unbound(XEN) IRQ: 11 affinity:1 vec:78 type=IO-APIC-edge status=00000002mapped, unbound(XEN) IRQ: 12 affinity:1 vec:88 type=IO-APIC-edge status=00000002mapped, unbound(XEN) IRQ: 13 affinity:f vec:90 type=IO-APIC-edge status=00000002mapped, unbound(XEN) IRQ: 14 affinity:1 vec:98 type=IO-APIC-edge status=00000002mapped, unbound(XEN) IRQ: 15 affinity:1 vec:a0 type=IO-APIC-edge status=00000002mapped, unbound(XEN) IRQ: 16 affinity:1 vec:b0 type=IO-APIC-level status=00000010in-flight=0 domain-list=0: 16(----),(XEN) IRQ: 17 affinity:1 vec:b8 type=IO-APIC-level status=00000010in-flight=0 domain-list=0: 17(----),(XEN) IRQ: 18 affinity:1 vec:a8 type=IO-APIC-level status=00000010in-flight=0 domain-list=0: 18(----),(XEN) IRQ: 19 affinity:f vec:d8 type=IO-APIC-level status=00000002mapped, unbound(XEN) IRQ: 24 affinity:1 vec:28 type=AMD-IOMMU-MSI status=00000000iommu_interrupt_handler+0/0x57(XEN) IRQ: 25 affinity:1 vec:c0 type=PCI-MSI status=00000010in-flight=0 domain-list=0:279(----),(XEN) IRQ: 26 affinity:1 vec:c8 type=PCI-MSI status=00000010in-flight=0 domain-list=0:278(----),(XEN) IRQ: 27 affinity:1 vec:d0 type=PCI-MSI status=00000010in-flight=0 domain-list=0:277(----),(XEN) IRQ: 28 affinity:1 vec:21 type=PCI-MSI status=00000010in-flight=0 domain-list=0:276(----),(XEN) IRQ: 29 affinity:1 vec:29 type=PCI-MSI/-X status=00000010in-flight=0 domain-list=0:275(----),(XEN) IRQ: 30 affinity:1 vec:31 type=PCI-MSI/-X status=00000010in-flight=0 domain-list=0:274(----),(XEN) IRQ: 31 affinity:1 vec:39 type=PCI-MSI/-X status=00000010in-flight=0 domain-list=0:273(----),(XEN) IRQ: 32 affinity:1 vec:41 type=PCI-MSI/-X status=00000010in-flight=0 domain-list=0:272(----),(XEN) IRQ: 33 affinity:1 vec:49 type=PCI-MSI/-X status=00000010in-flight=0 domain-list=0:271(----),(XEN) IRQ: 34 affinity:1 vec:51 type=PCI-MSI/-X status=00000010in-flight=0 domain-list=0:270(----),(XEN) IRQ: 35 affinity:1 vec:59 type=PCI-MSI status=00000010in-flight=0 domain-list=0:269(----),(XEN) IRQ: 36 affinity:1 vec:61 type=PCI-MSI status=00000010in-flight=0 domain-list=0:268(----),(XEN) IRQ: 37 affinity:1 vec:69 type=PCI-MSI status=00000010in-flight=0 domain-list=0:267(----),(XEN) IRQ: 38 affinity:1 vec:71 type=PCI-MSI status=00000010in-flight=0 domain-list=0:266(----),

(XEN) IO-APIC interrupt information:
(XEN)     IRQ  0 Vec240:

(XEN) Apic 0x00, Pin 2: vec=f0 delivery=Fixed dest=L status=0polarity=0 irr=0 trig=E mask=0 dest_id:1

(XEN)     IRQ  1 Vec 48:

(XEN) Apic 0x00, Pin 1: vec=b0 delivery=Fixed dest=L status=0polarity=0 irr=0 trig=E mask=0 dest_id:1

(XEN)     IRQ  3 Vec 56:

(XEN) Apic 0x00, Pin 3: vec=38 delivery=Fixed dest=L status=0polarity=0 irr=0 trig=E mask=0 dest_id:1

(XEN)     IRQ  4 Vec 64:

(XEN) Apic 0x00, Pin 4: vec=40 delivery=Fixed dest=L status=0polarity=0 irr=0 trig=E mask=0 dest_id:1

(XEN)     IRQ  5 Vec 72:

(XEN) Apic 0x00, Pin 5: vec=48 delivery=LoPri dest=L status=0polarity=0 irr=0 trig=E mask=1 dest_id:15

(XEN)     IRQ  6 Vec 80:

(XEN) Apic 0x00, Pin 6: vec=50 delivery=Fixed dest=L status=0polarity=0 irr=0 trig=E mask=0 dest_id:1

(XEN)     IRQ  7 Vec 88:

(XEN) Apic 0x00, Pin 7: vec=58 delivery=Fixed dest=L status=0polarity=0 irr=0 trig=E mask=0 dest_id:1

(XEN)     IRQ  8 Vec 96:

(XEN) Apic 0x00, Pin 8: vec=60 delivery=Fixed dest=L status=0polarity=0 irr=0 trig=E mask=0 dest_id:1

(XEN)     IRQ  9 Vec104:

(XEN) Apic 0x00, Pin 9: vec=68 delivery=Fixed dest=L status=0polarity=1 irr=0 trig=L mask=0 dest_id:1

(XEN)     IRQ 10 Vec112:

(XEN) Apic 0x00, Pin 10: vec=70 delivery=Fixed dest=L status=0polarity=0 irr=0 trig=E mask=0 dest_id:1

(XEN)     IRQ 11 Vec120:

(XEN) Apic 0x00, Pin 11: vec=78 delivery=Fixed dest=L status=0polarity=0 irr=0 trig=E mask=0 dest_id:1

(XEN)     IRQ 12 Vec136:

(XEN) Apic 0x00, Pin 12: vec=b0 delivery=Fixed dest=L status=0polarity=0 irr=0 trig=E mask=0 dest_id:1

(XEN)     IRQ 13 Vec144:

(XEN) Apic 0x00, Pin 13: vec=b0 delivery=Fixed dest=L status=0polarity=0 irr=0 trig=E mask=1 dest_id:15

(XEN)     IRQ 14 Vec152:

(XEN) Apic 0x00, Pin 14: vec=b0 delivery=Fixed dest=L status=0polarity=0 irr=0 trig=E mask=0 dest_id:1

(XEN)     IRQ 15 Vec160:

(XEN) Apic 0x00, Pin 15: vec=b0 delivery=Fixed dest=L status=0polarity=0 irr=0 trig=E mask=0 dest_id:1

(XEN)     IRQ 16 Vec176:

(XEN) Apic 0x00, Pin 16: vec=b0 delivery=Fixed dest=L status=0polarity=1 irr=0 trig=L mask=0 dest_id:1

(XEN)     IRQ 17 Vec184:

(XEN) Apic 0x00, Pin 17: vec=b0 delivery=Fixed dest=L status=0polarity=1 irr=1 trig=L mask=0 dest_id:1

(XEN)     IRQ 18 Vec168:

(XEN) Apic 0x00, Pin 18: vec=b0 delivery=Fixed dest=L status=0polarity=1 irr=1 trig=L mask=0 dest_id:1

(XEN)     IRQ 19 Vec216:

(XEN) Apic 0x00, Pin 19: vec=b0 delivery=Fixed dest=L status=0polarity=1 irr=0 trig=L mask=1 dest_id:15



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Follow-Ups:
- Re: [Xen-devel] [PATCH 1/6] AMD IOMMU: allocate IRTE entries instead of using a static mapping
  - From: Jan Beulich

References:
- [Xen-devel] [PATCH 0/6] x86/IOMMU: multi-vector MSI
  - From: Jan Beulich
- [Xen-devel] [PATCH 1/6] AMD IOMMU: allocate IRTE entries instead of using a static mapping
  - From: Jan Beulich
- Re: [Xen-devel] [PATCH 1/6] AMD IOMMU: allocate IRTE entries instead of using a static mapping
  - From: Suravee Suthikulanit

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