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[Date Prev][Date Next][Thread Prev][Thread Next][Date Index][Thread Index] [Xen-devel] [xen-unstable test] 17691: regressions - FAIL
flight 17691 xen-unstable real [real] http://www.chiark.greenend.org.uk/~xensrcts/logs/17691/ Regressions :-( Tests which did not succeed and are blocking, including tests which could not be run: build-i386 4 xen-build fail REGR. vs. 17686 build-amd64-pvops 4 kernel-build fail REGR. vs. 17686 build-i386-pvops 4 kernel-build fail REGR. vs. 17686 build-i386-oldkern 4 xen-build fail REGR. vs. 17686 build-amd64-oldkern 4 xen-build fail REGR. vs. 17686 Tests which did not succeed, but are not blocking: test-amd64-amd64-xl-pcipt-intel 1 xen-build-check(1) blocked n/a test-amd64-amd64-xl 1 xen-build-check(1) blocked n/a test-amd64-i386-xl-multivcpu 1 xen-build-check(1) blocked n/a test-amd64-i386-pv 1 xen-build-check(1) blocked n/a test-amd64-i386-xl-credit2 1 xen-build-check(1) blocked n/a test-amd64-i386-qemut-rhel6hvm-intel 1 xen-build-check(1) blocked n/a test-amd64-i386-qemuu-rhel6hvm-intel 1 xen-build-check(1) blocked n/a test-amd64-amd64-pv 1 xen-build-check(1) blocked n/a test-amd64-amd64-xl-sedf 1 xen-build-check(1) blocked n/a test-amd64-i386-rhel6hvm-amd 1 xen-build-check(1) blocked n/a test-amd64-i386-qemut-rhel6hvm-amd 1 xen-build-check(1) blocked n/a test-amd64-i386-qemuu-rhel6hvm-amd 1 xen-build-check(1) blocked n/a test-amd64-amd64-xl-sedf-pin 1 xen-build-check(1) blocked n/a test-amd64-amd64-xl-qemut-win7-amd64 1 xen-build-check(1) blocked n/a test-amd64-amd64-xl-qemuu-winxpsp3 1 xen-build-check(1) blocked n/a test-amd64-amd64-pair 1 xen-build-check(1) blocked n/a test-amd64-i386-xend-winxpsp3 1 xen-build-check(1) blocked n/a test-amd64-amd64-xl-win7-amd64 1 xen-build-check(1) blocked n/a test-amd64-i386-xl 1 xen-build-check(1) blocked n/a test-amd64-i386-xl-win7-amd64 1 xen-build-check(1) blocked n/a test-amd64-i386-xl-qemut-win7-amd64 1 xen-build-check(1) blocked n/a test-amd64-i386-rhel6hvm-intel 1 xen-build-check(1) blocked n/a test-amd64-amd64-xl-winxpsp3 1 xen-build-check(1) blocked n/a test-amd64-amd64-xl-qemut-winxpsp3 1 xen-build-check(1) blocked n/a test-amd64-i386-xl-winxpsp3-vcpus1 1 xen-build-check(1) blocked n/a test-amd64-i386-xend-qemut-winxpsp3 1 xen-build-check(1) blocked n/a test-amd64-i386-xl-qemut-winxpsp3-vcpus1 1 xen-build-check(1) blocked n/a test-amd64-i386-pair 1 xen-build-check(1) blocked n/a test-amd64-amd64-xl-qemuu-win7-amd64 1 xen-build-check(1) blocked n/a version targeted for testing: xen f03b5006f7e6e396746a56f5f563fb0f55cabc44 baseline version: xen d78dab3eca85f9ff14af55583d83829e96a76b76 ------------------------------------------------------------ People who touched revisions under test: "Zhang, Xiantao" <xiantao.zhang@xxxxxxxxx> Boris Ostrovsky <boris.ostrovsky@xxxxxxxxxx> Daniel De Graaf <dgdegra@xxxxxxxxxxxxx> Dietmar Hahn <dietmar.hahn@xxxxxxxxxxxxxx> Jan Beulich <jbeulich@xxxxxxxx> Jun Nakajima <jun.nakajima@xxxxxxxxx> Keir Fraser <keir@xxxxxxx> ------------------------------------------------------------ jobs: build-amd64 pass build-armhf pass build-i386 fail build-amd64-oldkern fail build-i386-oldkern fail build-amd64-pvops fail build-i386-pvops fail test-amd64-amd64-xl blocked test-amd64-i386-xl blocked test-amd64-i386-rhel6hvm-amd blocked test-amd64-i386-qemut-rhel6hvm-amd blocked test-amd64-i386-qemuu-rhel6hvm-amd blocked test-amd64-amd64-xl-qemut-win7-amd64 blocked test-amd64-i386-xl-qemut-win7-amd64 blocked test-amd64-amd64-xl-qemuu-win7-amd64 blocked test-amd64-amd64-xl-win7-amd64 blocked test-amd64-i386-xl-win7-amd64 blocked test-amd64-i386-xl-credit2 blocked test-amd64-amd64-xl-pcipt-intel blocked test-amd64-i386-rhel6hvm-intel blocked test-amd64-i386-qemut-rhel6hvm-intel blocked test-amd64-i386-qemuu-rhel6hvm-intel blocked test-amd64-i386-xl-multivcpu blocked test-amd64-amd64-pair blocked test-amd64-i386-pair blocked test-amd64-amd64-xl-sedf-pin blocked test-amd64-amd64-pv blocked test-amd64-i386-pv blocked test-amd64-amd64-xl-sedf blocked test-amd64-i386-xl-qemut-winxpsp3-vcpus1 blocked test-amd64-i386-xl-winxpsp3-vcpus1 blocked test-amd64-i386-xend-qemut-winxpsp3 blocked test-amd64-amd64-xl-qemut-winxpsp3 blocked test-amd64-amd64-xl-qemuu-winxpsp3 blocked test-amd64-i386-xend-winxpsp3 blocked test-amd64-amd64-xl-winxpsp3 blocked ------------------------------------------------------------ sg-report-flight on woking.cam.xci-test.com logs: /home/xc_osstest/logs images: /home/xc_osstest/images Logs, config files, etc. are available at http://www.chiark.greenend.org.uk/~xensrcts/logs Test harness code can be found at http://xenbits.xensource.com/gitweb?p=osstest.git;a=summary Not pushing. ------------------------------------------------------------ commit f03b5006f7e6e396746a56f5f563fb0f55cabc44 Author: Boris Ostrovsky <boris.ostrovsky@xxxxxxxxxx> Date: Mon Apr 15 11:28:30 2013 +0200 x86/AMD: Dump AMD VPMU info Dump VPMU registers on AMD in the 'q' keyhandler. Signed-off-by: Boris Ostrovsky <boris.ostrovsky@xxxxxxxxxx> commit 1df002bb2f218baee6fa4116fa8a7994a49daa91 Author: Boris Ostrovsky <boris.ostrovsky@xxxxxxxxxx> Date: Mon Apr 15 11:28:08 2013 +0200 x86/AMD: Clean up context_update() in AMD VPMU code Clean up context_update() in AMD VPMU code. Rename restore routine to "load" to be consistent with Intel code and with arch_vpmu_ops names Signed-off-by: Boris Ostrovsky <boris.ostrovsky@xxxxxxxxxx> Reviewed-by: Dietmar Hahn <dietmar.hahn@xxxxxxxxxxxxxx> commit 055898c9c61d462888941eaede436db4d335890e Author: Boris Ostrovsky <boris.ostrovsky@xxxxxxxxxx> Date: Mon Apr 15 11:27:32 2013 +0200 x86/VPMU: Save/restore VPMU only when necessary VPMU doesn't need to always be saved during context switch. If we are comming back to the same processor and no other VPCU has run here we can simply continue running. This is especailly useful on Intel processors where Global Control MSR is stored in VMCS, thus not requiring us to stop the counters during save operation. On AMD we need to explicitly stop the counters but we don't need to save them. Signed-off-by: Boris Ostrovsky <boris.ostrovsky@xxxxxxxxxx> Reviewed-by: Dietmar Hahn <dietmar.hahn@xxxxxxxxxxxxxx> Tested-by: Dietmar Hahn <dietmar.hahn@xxxxxxxxxxxxxx> commit 426368be82b0184df1b537bb659680026b747a50 Author: Boris Ostrovsky <boris.ostrovsky@xxxxxxxxxx> Date: Mon Apr 15 11:26:44 2013 +0200 x86/VPMU: Factor out VPMU common code Factor out common code from SVM amd VMX into VPMU. Signed-off-by: Boris Ostrovsky <boris.ostrovsky@xxxxxxxxxx> Reviewed-by: Dietmar Hahn <dietmar.hahn@xxxxxxxxxxxxxx> Tested-by: Dietmar Hahn <dietmar.hahn@xxxxxxxxxxxxxx> Acked-by: Jun Nakajima <jun.nakajima@xxxxxxxxx> commit c6037adc5c934b9ab97e532415302e50ece962d5 Author: Boris Ostrovsky <boris.ostrovsky@xxxxxxxxxx> Date: Mon Apr 15 11:25:57 2013 +0200 x86/VPMU: Add Haswell support Initialize VPMU on Haswell CPUs. Signed-off-by: Boris Ostrovsky <boris.ostrovsky@xxxxxxxxxx> Reviewed-by: Dietmar Hahn <dietmar.hahn@xxxxxxxxxxxxxx> commit 5fb2decd2d3a821a7e9cff8c53220eaa45557d8f Author: Boris Ostrovsky <boris.ostrovsky@xxxxxxxxxx> Date: Mon Apr 15 11:25:18 2013 +0200 x86/AMD: Stop counters on VPMU save Stop the counters during VPMU save operation since they shouldn't be running when VPCU that controls them is not. This also makes it unnecessary to check for overflow in context_restore() Set LVTPC vector before loading the context during vpmu_restore(). Otherwise it is possible to trigger an interrupt without proper vector. Signed-off-by: Boris Ostrovsky <boris.ostrovsky@xxxxxxxxxx> Reviewed-by: Dietmar Hahn <dietmar.hahn@xxxxxxxxxxxxxx> commit 176706746dee6ad72f6bf15d2b6093973c652d6b Author: Boris Ostrovsky <boris.ostrovsky@xxxxxxxxxx> Date: Mon Apr 15 11:24:52 2013 +0200 x86/AMD: Load context when attempting to read VPMU MSRs Load context (and mark it as LOADED) on any MSR access. This will allow us to always read the most up-to-date value of an MSR: guest may write into an MSR without enabling it (thus not marking the context as RUNNING) and then be migrated. Without first loading the context reading this MSR from HW will not match the pervious write since registers will not be loaded into HW in amd_vpmu_load(). In addition, we should be saving the context when it is LOADED, not RUNNING --- otherwise we need to save it any time it becomes non-RUNNING, which may be a frequent occurrence. Signed-off-by: Boris Ostrovsky <boris.ostrovsky@xxxxxxxxxx> Reviewed-by: Dietmar Hahn <dietmar.hahn@xxxxxxxxxxxxxx> commit 45773c5fb6346b1bc2a2ddcc6d19bd7f53ccabff Author: Boris Ostrovsky <boris.ostrovsky@xxxxxxxxxx> Date: Mon Apr 15 11:24:27 2013 +0200 x86/AMD: Do not intercept access to performance counters MSRs Access to performance counters and reads of event selects don't need to always be intercepted. Signed-off-by: Boris Ostrovsky <boris.ostrovsky@xxxxxxxxxx> Reviewed-by: Dietmar Hahn <dietmar.hahn@xxxxxxxxxxxxxx> commit 6f3c6d1ed8d2c8b6cd5d9689159e3647bf428dcd Author: Boris Ostrovsky <boris.ostrovsky@xxxxxxxxxx> Date: Mon Apr 15 11:23:25 2013 +0200 x86/AMD: Allow more fine-grained control of VMCB MSR Permission Map Currently VMCB's MSRPM can be updated to either intercept both reads and writes to an MSR or not intercept neither. In some cases we may want to be more selective and intercept one but not the other. Signed-off-by: Boris Ostrovsky <boris.ostrovsky@xxxxxxxxxx> Reviewed-by: Dietmar Hahn <dietmar.hahn@xxxxxxxxxxxxxx> commit 6a727d6be892ea5ff818446d96974bebdf8ac3a2 Author: Jan Beulich <jbeulich@xxxxxxxx> Date: Mon Apr 15 10:33:48 2013 +0200 IOMMU: allow MSI message to IRTE propagation to fail With the need to allocate multiple contiguous IRTEs for multi-vector MSI, the chance of failure here increases. While on the AMD side there's no allocation of IRTEs at present at all (and hence no way for this allocation to fail, which is going to change with a later patch in this series), VT-d already ignores an eventual error here, which this patch fixes. Signed-off-by: Jan Beulich <jbeulich@xxxxxxxx> Acked-by: "Zhang, Xiantao" <xiantao.zhang@xxxxxxxxx> commit 887885c17ada9c571a7a2cd71410876448d0610a Author: Daniel De Graaf <dgdegra@xxxxxxxxxxxxx> Date: Mon Apr 15 10:25:41 2013 +0200 MAINTAINERS: Add myself as XSM maintainer Signed-off-by: Daniel De Graaf <dgdegra@xxxxxxxxxxxxx> Acked-by: Keir Fraser <keir@xxxxxxx> Acked-by: Jan Beulich <jbeulich@xxxxxxxx> (qemu changes not included) _______________________________________________ Xen-devel mailing list Xen-devel@xxxxxxxxxxxxx http://lists.xen.org/xen-devel
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