Re: [Xen-devel] Different CPU flags between Dom0 and DomU?

["Liu, Jinsong" <jinsong.liu@xxxxxxxxx>]

Konrad Rzeszutek Wilk wrote:
> On Mon, Mar 04, 2013 at 02:09:06PM +0900, Choonho Son wrote:
>> Hi all,
>> 
>> I have a machine with Intel Xeon E5-2630. Intel E5-series supports
>> AVX(Advanced Vector eXtension). And Xen Hypervisor 4.1 also supports
>> AVX feature.
> 
> Lets CC the Intel folks since these two git commits point to them:
> 
> commit 25050f53be29518a3c9bdd0628333cd3121d2750
> Author: Liu, Jinsong <jinsong.liu@xxxxxxxxx>
> Date:   Tue Dec 6 11:27:18 2011 +0000
> 
>     X86: expose Intel new features to pv/hvm
> 
>     Intel recently release some new features, including
>     FMA/AVX2/BMI1/BMI2/LZCNT/MOVBE.
>     Refer to http://software.intel.com/file/36945
>     This patch expose these new features to pv and hvm.
> 
>     Signed-off-by: Liu, Jinsong <jinsong.liu@xxxxxxxxx>
>     Committed-by: Keir Fraser <keir@xxxxxxx>
> 
> commit 500161db50e3430026b5374462c1bdac00257abe
> Author: Liu, Jinsong <jinsong.liu@xxxxxxxxx>
> Date:   Thu Dec 1 12:21:24 2011 +0100
> 
>     X86: expose Intel new features to dom0
> 
>     This patch expose Intel new features to dom0, including
>     FMA/AVX2/BMI1/BMI2/LZCNT/MOVBE.
> 
>     Signed-off-by: Liu, Jinsong <jinsong.liu@xxxxxxxxx>
>     Committed-by: Jan Beulich <jbeulich@xxxxxxxx>
> 
> 
>> 
>> /proc/cpuinfo shows the supported features:
>> 
>> - Bare-metal Linux (/proc/cpuinfo)
>> flags           : fpu vme de pse tsc msr pae mce cx8 apic mtrr pge
>> mca cmov pat pse36 clflush dts acpi mmx fxsr sse sse2 ss ht tm pbe
>> syscall nx pdpe1gb rdtscp lm constant_tsc arch_perfmon pebs bts
>> rep_good xtopology nonstop_tsc aperfmperf pni pclmulqdq dtes64
>> monitor ds_cpl vmx smx est tm2 ssse3 cx16 xtpr pdcm dca sse4_1
>> sse4_2 x2apic popcnt aes xsave avx lahf_lm ida arat xsaveopt pln pts
>> dts tpr_shadow vnmi flexpriority ept vpid 
>> 
>> - Dom0 (/proc/cpuinfo)
>> flags           : fpu de tsc msr pae mce cx8 apic sep mca cmov pat
>> clflush acpi mmx fxsr sse sse2 ss ht syscall nx lm constant_tsc
>> rep_good nopl nonstop_tsc eagerfpu pni pclmulqdq monitor est ssse3
>> cx16 sse4_1 sse4_2 x2apic popcnt tsc_deadline_timer aes xsave avx
>> hypervisor lahf_lm ida arat xsaveopt pln pts dtherm
>> 
>> - DomU (/proc/cpuinfo)
>> flags           : fpu vme de pse tsc msr pae mce cx8 apic sep mtrr
>> pge mca cmov pat pse36 clflush mmx fxsr sse sse2 ht syscall nx
>> rdtscp lm constant_tsc pni ssse3 cx16 sse4_1 sse4_2 popcnt lahf_lm
>> 
>> 
>> [Questions]
>> 
>> 1) Why CPU flags are different among bare-metal, dom0, and domU? 2)
>> How can I use avx in DomU? 3) How CPU flags are delivered from
>> Dom0(or Hypervisor) to DomU? 
>> 

Sorry for late reply.

cpuid difference among bare-metal, dom0, and domU and depends on some factors.
For bare-metal it gets cpuid per h/w caps;
For dom0, cpuid basically get from h/w caps but controlled/filtered by 
hypervisor, considering some caps are not proper to expose (say, mwait), or 
some caps are purely emulated by s/w though not really support by h/w;
For domU it gets cpuid per the caps getting from hypervisor and caps exposing 
policy (via tools side) for purpose like live migration;

For cpuid exposing to guest refer to
* tools side: xc_cpuid_apply_policy()
* hypervisor side: pv_cpuid() and domain_cpuid()    // pv get cpuid via UD2/GP, 
hvm get cpuid via vmexit

Thanks,
Jinsong
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