Re: [Xen-devel] [PATCH 13/45] xen: arm64: dcache flush

[Tim Deegan <tim@xxxxxxx>]

At 16:45 +0000 on 08 Feb (1360341915), Ian Campbell wrote:
> Subject: [PATCH] xen: arm64: dcache flush
> 
> Use "dsb sy" instead of bare "dsb", they mean the same on 32-bit but only the
> former is valid on 64-bit.
> 
> Abstract the actual flush operation into a macro.
> 
> Signed-off-by: Ian Campbell <ian.campbell@xxxxxxxxxx>

Acked-by: Tim Deegan <tim@xxxxxxx>

> ---
> v2: revert to inline asm
> ---
>  xen/include/asm-arm/arm32/page.h |    3 +++
>  xen/include/asm-arm/arm64/page.h |    3 +++
>  xen/include/asm-arm/page.h       |    8 ++++----
>  3 files changed, 10 insertions(+), 4 deletions(-)
> 
> diff --git a/xen/include/asm-arm/arm32/page.h 
> b/xen/include/asm-arm/arm32/page.h
> index 96b5798..45d25ee 100644
> --- a/xen/include/asm-arm/arm32/page.h
> +++ b/xen/include/asm-arm/arm32/page.h
> @@ -23,6 +23,9 @@ static inline void write_pte(lpae_t *p, lpae_t pte)
>          : : "r" (pte.bits), "r" (p) : "memory");
>  }
>  
> +/* Inline ASM to flush dcache on register R (may be an inline asm operand) */
> +#define __flush_xen_dcache_one(R) STORE_CP32(R, DCCMVAC)
> +
>  /*
>   * Flush all hypervisor mappings from the TLB and branch predictor.
>   * This is needed after changing Xen code mappings.
> diff --git a/xen/include/asm-arm/arm64/page.h 
> b/xen/include/asm-arm/arm64/page.h
> index ce5be63..1d7c70e 100644
> --- a/xen/include/asm-arm/arm64/page.h
> +++ b/xen/include/asm-arm/arm64/page.h
> @@ -18,6 +18,9 @@ static inline void write_pte(lpae_t *p, lpae_t pte)
>          : : "r" (pte.bits), "r" (p) : "memory");
>  }
>  
> +/* Inline ASM to flush dcache on register R (may be an inline asm operand) */
> +#define __flush_xen_dcache_one(R) "dc cvac, %" #R ";"
> +
>  /*
>   * Flush all hypervisor mappings from the TLB
>   * This is needed after changing Xen code mappings.
> diff --git a/xen/include/asm-arm/page.h b/xen/include/asm-arm/page.h
> index 4e245a9..b89238b 100644
> --- a/xen/include/asm-arm/page.h
> +++ b/xen/include/asm-arm/page.h
> @@ -251,7 +251,7 @@ static inline void flush_xen_dcache_va_range(void *p, 
> unsigned long size)
>      void *end;
>      dsb();           /* So the CPU issues all writes to the range */
>      for ( end = p + size; p < end; p += cacheline_bytes )
> -        WRITE_CP32((uint32_t) p, DCCMVAC);
> +        asm volatile (__flush_xen_dcache_one(0) : : "r" (p));
>      dsb();           /* So we know the flushes happen before continuing */
>  }
>  
> @@ -264,9 +264,9 @@ static inline void flush_xen_dcache_va_range(void *p, 
> unsigned long size)
>          flush_xen_dcache_va_range(_p, sizeof(x));                       \
>      else                                                                \
>          asm volatile (                                                  \
> -            "dsb;"   /* Finish all earlier writes */                    \
> -            STORE_CP32(0, DCCMVAC)                                      \
> -            "dsb;"   /* Finish flush before continuing */               \
> +            "dsb sy;"   /* Finish all earlier writes */                 \
> +            __flush_xen_dcache_one(0)                                   \
> +            "dsb sy;"   /* Finish flush before continuing */            \
>              : : "r" (_p), "m" (*_p));                                   \
>  } while (0)
>  
> -- 
> 1.7.2.5
> 
> 
> 
> 
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