Re: [Xen-devel] [PATCH v3 2/2] Xen: Fix VMCS setting for x2APIC mode guest while enabling APICV

["Jan Beulich" <JBeulich@xxxxxxxx>]

>>> On 28.01.13 at 05:13, "Li, Jiongxi" <jiongxi.li@xxxxxxxxx> wrote:
> @@ -673,6 +674,36 @@ void vmx_disable_intercept_for_msr(struct vcpu *v, u32 
> msr, int type)
>      }
>  }
>  
> +void vmx_enable_intercept_for_msr(struct vcpu *v, u32 msr, int type)
> +{
> +    unsigned long *msr_bitmap = v->arch.hvm_vmx.msr_bitmap;
> +
> +    /* VMX MSR bitmap supported? */
> +    if ( msr_bitmap == NULL )
> +        return;
> +
> +    /*
> +     * See Intel PRM Vol. 3, 20.6.9 (MSR-Bitmap Address). Early manuals
> +     * have the write-low and read-high bitmap offsets the wrong way round.
> +     * We can control MSRs 0x00000000-0x00001fff and 0xc0000000-0xc0001fff.
> +     */
> +    if ( msr <= 0x1fff )
> +    {
> +        if (type & MSR_TYPE_R)
> +            __set_bit(msr, msr_bitmap + 0x000/BYTES_PER_LONG); /* read-low */
> +        if (type & MSR_TYPE_W)
> +            __set_bit(msr, msr_bitmap + 0x800/BYTES_PER_LONG); /* write-low 
> */
> +    }
> +    else if ( (msr >= 0xc0000000) && (msr <= 0xc0001fff) )
> +    {
> +        msr &= 0x1fff;
> +        if (type & MSR_TYPE_R)
> +            __set_bit(msr, msr_bitmap + 0x400/BYTES_PER_LONG); /* read-high 
> */
> +        if (type & MSR_TYPE_W)
> +            __set_bit(msr, msr_bitmap + 0xc00/BYTES_PER_LONG); /* write-high 
> */
> +    }

I'm afraid that now that this and its "disable" counterpart aren't
being used exclusively from construct_vmcs() anymore, you can't
use __set_bit()/__clear_bit() here/there.

Jan


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