[Xen-devel] [PATCH 10/10] nested vmx: check host ability when intercept MSR read

[Dongxiao Xu <dongxiao.xu@xxxxxxxxx>]

When guest hypervisor tries to read MSR value, we intercept this behavior
and return certain emulated values. Besides that, we also need to ensure
that those emulated values must compatible with host ability.

Signed-off-by: Dongxiao Xu <dongxiao.xu@xxxxxxxxx>
---
 xen/arch/x86/hvm/vmx/vvmx.c |   19 ++++++++++++++-----
 1 files changed, 14 insertions(+), 5 deletions(-)

diff --git a/xen/arch/x86/hvm/vmx/vvmx.c b/xen/arch/x86/hvm/vmx/vvmx.c
index bbf5266..f2bba1b 100644
--- a/xen/arch/x86/hvm/vmx/vvmx.c
+++ b/xen/arch/x86/hvm/vmx/vvmx.c
@@ -1319,19 +1319,20 @@ int nvmx_handle_vmwrite(struct cpu_user_regs *regs)
  */
 int nvmx_msr_read_intercept(unsigned int msr, u64 *msr_content)
 {
-    u64 data = 0, tmp = 0;
+    u64 data = 0, host_data = 0, tmp = 0;
     int r = 1;
 
     if ( !nestedhvm_enabled(current->domain) )
         return 0;
 
+    rdmsrl(msr, host_data);
+
     /*
      * Remove unsupport features from n1 guest capability MSR
      */
     switch (msr) {
     case MSR_IA32_VMX_BASIC:
-        data = VVMCS_REVISION | ((u64)PAGE_SIZE) << 32 | 
-               ((u64)MTRR_TYPE_WRBACK) << 50 | (1ULL << 55);
+        data = (host_data & (~0ul << 32)) | VVMCS_REVISION;
         break;
     case MSR_IA32_VMX_PINBASED_CTLS:
     case MSR_IA32_VMX_TRUE_PINBASED_CTLS:
@@ -1342,6 +1343,8 @@ int nvmx_msr_read_intercept(unsigned int msr, u64 
*msr_content)
         /* Consult SDM for default1 setting */
         tmp = ( (1<<1) | (1<<2) | (1<<4) );
         data = ((data | tmp) << 32) | (tmp);
+        data = ((data & host_data) & (~0ul << 32)) |
+               ((data | host_data) & (~0u));
         break;
     case MSR_IA32_VMX_PROCBASED_CTLS:
     case MSR_IA32_VMX_TRUE_PROCBASED_CTLS:
@@ -1373,7 +1376,8 @@ int nvmx_msr_read_intercept(unsigned int msr, u64 
*msr_content)
             tmp = 0x4006172;
         /* 0-settings */
         data = ((data | tmp) << 32) | (tmp);
-
+        data = ((data & host_data) & (~0ul << 32)) |
+               ((data | host_data) & (~0u));
         break;
     case MSR_IA32_VMX_PROCBASED_CTLS2:
         /* 1-seetings */
@@ -1382,6 +1386,8 @@ int nvmx_msr_read_intercept(unsigned int msr, u64 
*msr_content)
         /* 0-settings */
         tmp = 0;
         data = (data << 32) | tmp;
+        data = ((data & host_data) & (~0ul << 32)) |
+               ((data | host_data) & (~0u));
         break;
     case MSR_IA32_VMX_EXIT_CTLS:
     case MSR_IA32_VMX_TRUE_EXIT_CTLS:
@@ -1400,6 +1406,8 @@ int nvmx_msr_read_intercept(unsigned int msr, u64 
*msr_content)
                VM_EXIT_LOAD_PERF_GLOBAL_CTRL;
        /* 0-settings */
         data = ((data | tmp) << 32) | tmp;
+        data = ((data & host_data) & (~0ul << 32)) |
+               ((data | host_data) & (~0u));
         break;
     case MSR_IA32_VMX_ENTRY_CTLS:
     case MSR_IA32_VMX_TRUE_ENTRY_CTLS:
@@ -1413,8 +1421,9 @@ int nvmx_msr_read_intercept(unsigned int msr, u64 
*msr_content)
                VM_ENTRY_LOAD_PERF_GLOBAL_CTRL |
                VM_ENTRY_IA32E_MODE;
         data = ((data | tmp) << 32) | tmp;
+        data = ((data & host_data) & (~0ul << 32)) |
+               ((data | host_data) & (~0u));
         break;
-
     case IA32_FEATURE_CONTROL_MSR:
         data = IA32_FEATURE_CONTROL_MSR_LOCK | 
                IA32_FEATURE_CONTROL_MSR_ENABLE_VMXON_OUTSIDE_SMX;
-- 
1.7.1


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