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[Xen-devel] [xen-unstable test] 14403: regressions - FAIL



flight 14403 xen-unstable real [real]
http://www.chiark.greenend.org.uk/~xensrcts/logs/14403/

Regressions :-(

Tests which did not succeed and are blocking,
including tests which could not be run:
 test-amd64-amd64-xl-qemuu-win7-amd64  7 windows-install   fail REGR. vs. 14399

Regressions which are regarded as allowable (not blocking):
 test-amd64-amd64-xl-sedf-pin 10 guest-saverestore            fail   like 14399
 test-amd64-amd64-xl-sedf      5 xen-boot                     fail   like 14399
 test-amd64-amd64-xl-qemuu-winxpsp3  9 guest-localmigrate       fail like 14399

Tests which did not succeed, but are not blocking:
 test-amd64-amd64-xl-pcipt-intel  9 guest-start                 fail never pass
 test-amd64-i386-xend-winxpsp3 16 leak-check/check             fail  never pass
 test-amd64-i386-win          16 leak-check/check             fail   never pass
 test-amd64-i386-xl-win-vcpus1 13 guest-stop                   fail  never pass
 test-amd64-amd64-xl-win7-amd64 13 guest-stop                   fail never pass
 test-amd64-i386-win-vcpus1   16 leak-check/check             fail   never pass
 test-amd64-i386-xl-win7-amd64 13 guest-stop                   fail  never pass
 test-amd64-amd64-xl-winxpsp3 13 guest-stop                   fail   never pass
 test-amd64-i386-xl-winxpsp3-vcpus1 13 guest-stop               fail never pass
 test-amd64-amd64-xl-win      13 guest-stop                   fail   never pass
 test-amd64-amd64-win         16 leak-check/check             fail   never pass

version targeted for testing:
 xen                  321f8487379b
baseline version:
 xen                  d1d05cb59a76

------------------------------------------------------------
People who touched revisions under test:
  Andre Przywara <osp@xxxxxxxxx>
  Andrew Cooper <andrew.cooper3@xxxxxxxxxx>
  Boris Ostrovsky <boris.ostrovsky@xxxxxxx>
  Christoph Egger <Christoph_Egger@xxxxxx>
  Ian Campbell <ian.campbell@xxxxxxxxxx>
  Jim Fehlig <jfehlig@xxxxxxxx>
  Keir Fraser <keir@xxxxxxx>
  Stefano Stabellini <stefano.stabellini@xxxxxxxxxxxxx>
  Tim Deegan <tim@xxxxxxx>
  Wei Huang <wei.huang2@xxxxxxx>
  Wei Wang <weiwang.dd@xxxxxxxxx>
------------------------------------------------------------

jobs:
 build-amd64                                                  pass    
 build-i386                                                   pass    
 build-amd64-oldkern                                          pass    
 build-i386-oldkern                                           pass    
 build-amd64-pvops                                            pass    
 build-i386-pvops                                             pass    
 test-amd64-amd64-xl                                          pass    
 test-amd64-i386-xl                                           pass    
 test-amd64-i386-rhel6hvm-amd                                 pass    
 test-amd64-i386-qemuu-rhel6hvm-amd                           pass    
 test-amd64-amd64-xl-qemuu-win7-amd64                         fail    
 test-amd64-amd64-xl-win7-amd64                               fail    
 test-amd64-i386-xl-win7-amd64                                fail    
 test-amd64-i386-xl-credit2                                   pass    
 test-amd64-amd64-xl-pcipt-intel                              fail    
 test-amd64-i386-rhel6hvm-intel                               pass    
 test-amd64-i386-qemuu-rhel6hvm-intel                         pass    
 test-amd64-i386-xl-multivcpu                                 pass    
 test-amd64-amd64-pair                                        pass    
 test-amd64-i386-pair                                         pass    
 test-amd64-amd64-xl-sedf-pin                                 fail    
 test-amd64-amd64-pv                                          pass    
 test-amd64-i386-pv                                           pass    
 test-amd64-amd64-xl-sedf                                     fail    
 test-amd64-i386-win-vcpus1                                   fail    
 test-amd64-i386-xl-win-vcpus1                                fail    
 test-amd64-i386-xl-winxpsp3-vcpus1                           fail    
 test-amd64-amd64-win                                         fail    
 test-amd64-i386-win                                          fail    
 test-amd64-amd64-xl-win                                      fail    
 test-amd64-amd64-xl-qemuu-winxpsp3                           fail    
 test-amd64-i386-xend-winxpsp3                                fail    
 test-amd64-amd64-xl-winxpsp3                                 fail    


------------------------------------------------------------
sg-report-flight on woking.cam.xci-test.com
logs: /home/xc_osstest/logs
images: /home/xc_osstest/images

Logs, config files, etc. are available at
    http://www.chiark.greenend.org.uk/~xensrcts/logs

Test harness code can be found at
    http://xenbits.xensource.com/gitweb?p=osstest.git;a=summary


Not pushing.

------------------------------------------------------------
changeset:   26160:321f8487379b
tag:         tip
user:        Stefano Stabellini <stefano.stabellini@xxxxxxxxxxxxx>
date:        Thu Nov 15 10:25:29 2012 +0000
    
    xen/arm: wake up secondary cpus
    
    Secondary cpus are held by the firmware until we send an IPI to them.
    
    Reordered non-boot cpu wait loop to perform the check before waiting
    for an event, to handled the case where the event has already
    happened when we reach the loop.
    
    Signed-off-by: Stefano Stabellini <stefano.stabellini@xxxxxxxxxxxxx>
    Acked-by: Ian Campbell <ian.campbell@xxxxxxxxxx>
    Committed-by: Ian Campbell <ian.campbell@xxxxxxxxxx>
    
    
changeset:   26159:5718bbed558b
user:        Stefano Stabellini <stefano.stabellini@xxxxxxxxxxxxx>
date:        Thu Nov 15 10:25:28 2012 +0000
    
    xen/arm: set the SMP bit in the ACTLR register
    
    "Enables the processor to receive instruction cache, BTB, and TLB 
maintenance
    operations from other processors"
    
    ...
    
    "You must set this bit before enabling the caches and MMU, or
    performing any cache and TLB maintenance operations. The only time
    you must clear this bit is during a processor power-down sequence"
    
    Signed-off-by: Stefano Stabellini <stefano.stabellini@xxxxxxxxxxxxx>
    Acked-by: Tim Deegan <tim@xxxxxxx>
    Committed-by: Ian Campbell <ian.campbell@xxxxxxxxxx>
    
    
changeset:   26158:999fae11df23
user:        Stefano Stabellini <stefano.stabellini@xxxxxxxxxxxxx>
date:        Thu Nov 15 10:25:27 2012 +0000
    
    pl011: set baud and clock_hz to the right defaults for Versatile Express
    
    Signed-off-by: Stefano Stabellini <stefano.stabellini@xxxxxxxxxxxxx>
    Acked-by: Tim Deegan <tim@xxxxxxx>
    Committed-by: Ian Campbell <ian.campbell@xxxxxxxxxx>
    
    
changeset:   26157:2312d29744e3
user:        Stefano Stabellini <stefano.stabellini@xxxxxxxxxxxxx>
date:        Thu Nov 15 10:25:26 2012 +0000
    
    xen/arm: setup the fixmap in head.S
    
    Setup the fixmap mapping directly in head.S rather than having a
    temporary mapping only to re-do it later in C.
    
    Signed-off-by: Stefano Stabellini <stefano.stabellini@xxxxxxxxxxxxx>
    Acked-by: Ian Campbell <ian.campbell@xxxxxxxxxx>
    Committed-by: Ian Campbell <ian.campbell@xxxxxxxxxx>
    
    
changeset:   26156:008726e63e7d
user:        Stefano Stabellini <stefano.stabellini@xxxxxxxxxxxxx>
date:        Thu Nov 15 10:25:26 2012 +0000
    
    xen/arm: pass the correct bit-per-interrupt argument to vgic_irq_rank
    
    Use 1 for registers that have 1 bit per irq.
    
    Signed-off-by: Stefano Stabellini <stefano.stabellini@xxxxxxxxxxxxx>
    Acked-by: Ian Campbell <ian.campbell@xxxxxxxxxx>
    Committed-by: Ian Campbell <ian.campbell@xxxxxxxxxx>
    
    
changeset:   26155:babb84d9a82e
user:        Jim Fehlig <jfehlig@xxxxxxxx>
date:        Thu Nov 15 10:25:25 2012 +0000
    
    libxl: Fix passing of application data to timeout_deregister hook
    
    When deregistering a timeout, the address of application data was
    being passed to the timeout_deregister hook instead of the data
    itself.
    
    Signed-off-by: Jim Fehlig <jfehlig@xxxxxxxx>
    Acked-by: Ian Campbell <ian.campbell@xxxxxxxxxx>
    Committed-by: Ian Campbell <ian.campbell@xxxxxxxxxx>
    
    
changeset:   26154:b9b4456e12d1
user:        Andrew Cooper <andrew.cooper3@xxxxxxxxxx>
date:        Thu Nov 15 09:54:38 2012 +0000
    
    x86/nmi: self_nmi() should not unconditionally enable interrupts
    
    It seems that all current callers have interrupts enabled, making the
    code currently safe but dangerous.  Also, fix a trailing whitespace
    issue.
    
    Signed-off-by: Andrew Cooper <andrew.cooper3@xxxxxxxxxx>
    Committed-by: Keir Fraser <keir@xxxxxxx>
    
    
changeset:   26153:f50e2f4278ab
user:        Andre Przywara <osp@xxxxxxxxx>
date:        Thu Nov 15 09:52:12 2012 +0000
    
    update MAINTAINERS file
    
    There have been some "organizational changes" within AMD.
    Update the MAINTAINERS file accordingly.
    Please also feel free to use the new email addresses if there are
    any inquires related to code authored by Wei Wang, Christoph Egger
    or Andre Przywara.
    
    Signed-off-by: Andre Przywara <osp@xxxxxxxxx>
    Acked-by: Wei Wang <weiwang.dd@xxxxxxxxx>
    Acked-by: Boris Ostrovsky <boris.ostrovsky@xxxxxxx>
    Acked-by: Wei Huang <wei.huang2@xxxxxxx>
    Acked-by: Christoph Egger <Christoph_Egger@xxxxxx>
    Committed-by: Keir Fraser <keir@xxxxxxx>
    
    
changeset:   26152:d1d05cb59a76
user:        Ian Campbell <ian.campbell@xxxxxxxxxx>
date:        Wed Nov 14 16:27:58 2012 +0000
    
    tools: rerun autoconf after 26144:170d45f7a2eb
    
    Signed-off-by: Ian Campbell <ian.campbell@xxxxxxxxxx>
    Committed-by: Ian Campbell <ian.campbell@xxxxxxxxxx>
    
    
(qemu changes not included)

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