# User Christoph Egger
# Date 1350465050 -7200
implement AMD MSRs for vMCE

Signed-off-by: Christoph Egger <Christoph.Egger@xxxxxxx>

diff -r 9181f580bc3f -r 7d79c4a86be5 xen/arch/x86/cpu/mcheck/amd_f10.c
--- a/xen/arch/x86/cpu/mcheck/amd_f10.c
+++ b/xen/arch/x86/cpu/mcheck/amd_f10.c
@@ -106,24 +106,43 @@ enum mcheck_type amd_f10_mcheck_init(str
 /* amd specific MCA MSR */
 int vmce_amd_wrmsr(struct vcpu *v, uint32_t msr, uint64_t val)
 {
-        switch (msr) {
-        case MSR_F10_MC4_MISC1:
-        case MSR_F10_MC4_MISC2:
-        case MSR_F10_MC4_MISC3:
-                break;
-        }
+	switch (msr) {
+	case MSR_F10_MC4_MISC1: /* DRAM error type */
+		v->arch.vmce.bank[1].mci_misc = val; 
+		mce_printk(MCE_VERBOSE, "MCE: wr msr %#"PRIx64"\n", val);
+		break;
+	case MSR_F10_MC4_MISC2: /* Link error type */
+	case MSR_F10_MC4_MISC3: /* L3 cache error type */
+		/* ignore write: we do not emulate link and l3 cache errors
+		 * to the guest.
+		 */
+		mce_printk(MCE_VERBOSE, "MCE: wr msr %#"PRIx64"\n", val);
+		break;
+	default:
+		return 0;
+	}
 
-        return 1;
+	return 1;
 }
 
 int vmce_amd_rdmsr(const struct vcpu *v, uint32_t msr, uint64_t *val)
 {
-        switch (msr) {
-        case MSR_F10_MC4_MISC1:
-        case MSR_F10_MC4_MISC2:
-        case MSR_F10_MC4_MISC3:
-                break;
-        }
+	switch (msr) {
+	case MSR_F10_MC4_MISC1: /* DRAM error type */
+		*val = v->arch.vmce.bank[1].mci_misc;
+		mce_printk(MCE_VERBOSE, "MCE: rd msr %#"PRIx64"\n", *val);
+		break;
+	case MSR_F10_MC4_MISC2: /* Link error type */
+	case MSR_F10_MC4_MISC3: /* L3 cache error type */
+		/* we do not emulate link and l3 cache
+		 * errors to the guest.
+		 */
+		*val = 0;
+		mce_printk(MCE_VERBOSE, "MCE: rd msr %#"PRIx64"\n", *val);
+		break;
+	default:
+		return 0;
+	}
 
-        return 1;
+	return 1;
 }