# User Christoph Egger
# Date 1348750048 -7200
Implement recoverable_scan() for AMD

Signed-off-by: Christoph Egger <Christoph.Egger@xxxxxxx>

diff -r af8840f1d82d -r 9b057c716549 xen/arch/x86/cpu/mcheck/Makefile
--- a/xen/arch/x86/cpu/mcheck/Makefile
+++ b/xen/arch/x86/cpu/mcheck/Makefile
@@ -2,6 +2,7 @@ obj-y += amd_nonfatal.o
 obj-y += k7.o
 obj-y += amd_k8.o
 obj-y += amd_f10.o
+obj-y += mce_amd.o
 obj-y += barrier.o
 obj-y += mctelem.o
 obj-y += mce.o
diff -r af8840f1d82d -r 9b057c716549 xen/arch/x86/cpu/mcheck/amd_f10.c
--- a/xen/arch/x86/cpu/mcheck/amd_f10.c
+++ b/xen/arch/x86/cpu/mcheck/amd_f10.c
@@ -37,18 +37,13 @@
 
 #include <xen/init.h>
 #include <xen/types.h>
-#include <xen/kernel.h>
-#include <xen/config.h>
-#include <xen/smp.h>
 
-#include <asm/processor.h>
-#include <asm/system.h>
 #include <asm/msr.h>
 
 #include "mce.h"
 #include "mce_quirks.h"
 #include "x86_mca.h"
-
+#include "mce_amd.h"
 
 static struct mcinfo_extended *
 amd_f10_handler(struct mc_info *mi, uint16_t bank, uint64_t status)
@@ -89,6 +84,11 @@ amd_f10_handler(struct mc_info *mi, uint
 	return mc_ext;
 }
 
+static int amd_f10_recoverable_scan(uint64_t status)
+{
+	return mc_amd_recoverable_scan(status);
+}
+
 /* AMD Family10 machine check */
 enum mcheck_type amd_f10_mcheck_init(struct cpuinfo_x86 *c)
 { 
@@ -101,6 +101,7 @@ enum mcheck_type amd_f10_mcheck_init(str
 		mcequirk_amd_apply(quirkflag);
 
 	x86_mce_callback_register(amd_f10_handler);
+	mce_recoverable_register(amd_f10_recoverable_scan);
 
 	return mcheck_amd_famXX;
 }
diff -r af8840f1d82d -r 9b057c716549 xen/arch/x86/cpu/mcheck/mce.h
--- a/xen/arch/x86/cpu/mcheck/mce.h
+++ b/xen/arch/x86/cpu/mcheck/mce.h
@@ -73,7 +73,7 @@ extern void mcheck_cmn_handler(struct cp
     struct mca_banks *, struct mca_banks *);
 
 /* Register a handler for judging whether mce is recoverable. */
-typedef int (*mce_recoverable_t)(u64 status);
+typedef int (*mce_recoverable_t)(uint64_t status);
 extern void mce_recoverable_register(mce_recoverable_t);
 
 /* Read an MSR, checking for an interposed value first */
diff -r af8840f1d82d -r 9b057c716549 xen/arch/x86/cpu/mcheck/mce_amd.c
--- /dev/null
+++ b/xen/arch/x86/cpu/mcheck/mce_amd.c
@@ -0,0 +1,76 @@
+/*
+ * common MCA implementation for AMD CPUs.
+ * Copyright (c) 2012 Advanced Micro Devices, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
+ */
+
+#include <xen/init.h>
+#include <xen/types.h>
+
+#include <asm/msr.h>
+
+#include "mce.h"
+#include "x86_mca.h"
+#include "mce_amd.h"
+
+/* Error Code Types */
+enum mc_ec_type {
+    MC_EC_TLB_TYPE = 0x0010,
+    MC_EC_MEM_TYPE = 0x0100,
+    MC_EC_BUS_TYPE = 0x0800,
+};
+
+enum mc_ec_type
+mc_ec2type(uint16_t errorcode)
+{
+    if ((errorcode & MC_EC_BUS_TYPE) == MC_EC_BUS_TYPE)
+        return MC_EC_BUS_TYPE;
+    if ((errorcode & MC_EC_MEM_TYPE) == MC_EC_MEM_TYPE)
+        return MC_EC_MEM_TYPE;
+    if ((errorcode & MC_EC_TLB_TYPE) == MC_EC_TLB_TYPE)
+        return MC_EC_TLB_TYPE;
+    /* Unreached */
+    BUG();
+    return 0;
+}
+
+int
+mc_amd_recoverable_scan(uint64_t status)
+{
+    int ret = 0;
+    enum mc_ec_type ectype;
+    uint16_t errorcode;
+
+    if ( !(status & MCi_STATUS_UC) )
+        return 1;
+
+    errorcode = status & (MCi_STATUS_MCA | MCi_STATUS_MSEC);
+    ectype = mc_ec2type(errorcode);
+
+    switch (ectype) {
+    case MC_EC_BUS_TYPE: /* value in addr MSR is physical */
+        /* should run cpu offline action */
+        break;
+    case MC_EC_MEM_TYPE: /* value in addr MSR is physical */
+        ret = 1; /* run memory page offline action */
+        break;
+    case MC_EC_TLB_TYPE: /* value in addr MSR is virtual */
+        /* should run tlb flush action and retry */
+        break;
+    }
+
+    return ret;
+}
diff -r af8840f1d82d -r 9b057c716549 xen/arch/x86/cpu/mcheck/mce_amd.h
--- /dev/null
+++ b/xen/arch/x86/cpu/mcheck/mce_amd.h
@@ -0,0 +1,6 @@
+#ifndef _MCHECK_AMD_H
+#define _MCHECK_AMD_H
+
+int mc_amd_recoverable_scan(uint64_t status);
+
+#endif
diff -r af8840f1d82d -r 9b057c716549 xen/arch/x86/cpu/mcheck/mce_intel.c
--- a/xen/arch/x86/cpu/mcheck/mce_intel.c
+++ b/xen/arch/x86/cpu/mcheck/mce_intel.c
@@ -560,7 +560,7 @@ static int intel_need_clearbank_scan(enu
  * 4) SRAO ser_support = 1, PCC = 0, S = 1, AR = 0, EN = 1 [UC = 1]
  * 5) UCNA ser_support = 1, OVER = 0, EN = 1, PCC = 0, S = 0, AR = 0, [UC = 1]
  */
-static int intel_recoverable_scan(u64 status)
+static int intel_recoverable_scan(uint64_t status)
 {
 
     if ( !(status & MCi_STATUS_UC ) )