Re: [Xen-devel] [PATCH 0/3] tsc adjust implementation for hvm

[Keir Fraser <keir@xxxxxxx>]

On 20/09/2012 09:06, "Liu, Jinsong" <jinsong.liu@xxxxxxxxx> wrote:

> Intel recently release a new tsc adjust feature at latest SDM 17.13.3.
> CPUID.7.0.EBX[1]=1 indicates TSC_ADJUST MSR 0x3b is supported.
> 
> Basically it is used to simplify TSC synchronization, operation of
> IA32_TSC_ADJUST MSR is as follows:
> 1). On RESET, the value of the IA32_TSC_ADJUST MSR is 0;
> 2). If an execution of WRMSR to the IA32_TIME_STAMP_COUNTER MSR adds (or
> subtracts)
>     value X from the TSC, the logical processor also adds (or subtracts) value
> X
>     from the IA32_TSC_ADJUST MSR;
> 3). If an execution of WRMSR to the IA32_TSC_ADJUST MSR adds (or subtracts)
>     value X from that MSR, the logical processor also adds (or subtracts)
> value X
>     from the TSC;
> 
> With it, OS would be easier when sync tsc.

Actually it appears to strictly add code to, and hence complicate, the
hypervisor. So how exactly is it beneficial?

 -- Keir

> Thanks,
> Jinsong



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