Re: [Xen-devel] [PATCH 1/3] xen/tools: Add 64 bits big bar support

["Hao, Xudong" <xudong.hao@xxxxxxxxx>]

> -----Original Message-----
> From: Jan Beulich [mailto:jbeulich@xxxxxxxx]
> Sent: Wednesday, August 22, 2012 3:32 PM
> To: Hao, Xudong
> Cc: ian.jackson@xxxxxxxxxxxxx; Zhang, Xiantao; xen-devel@xxxxxxxxxxxxx
> Subject: RE: [Xen-devel] [PATCH 1/3] xen/tools: Add 64 bits big bar support
> 
> >>> "Hao, Xudong" <xudong.hao@xxxxxxxxx> 08/22/12 3:03 AM >>>
> >> > Where does present the 36-bit physical addresses limit, could you help to
> >> > point out in the current Xen code?
> >>
> >> Look at xen/arch/x86/hvm/mtrr.c, e.g. hvm_mtrr_pat_init() or
> >> mtrr_var_range_msr_set().
> >
> > So if common 36-bit(guest) physical address could not change, can we use
> > top down from 64G, Jan, do you have any suggestion?
> 
> Sorry, I already said that I think the only viable option is top down from
> top of physical address space. No new address space holes please if at
> all possible - just do it in ways real firmware would do it (which would
> unlikely alter the RAM layout for this purpose).
> 

If the PCIe device has 64G bar size or more, how to do in current 36 bit, will 
we consider to extend the guest physical address? 
The real physical address space larger than 40 bit, there is not this issue.


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