Re: [Xen-devel] Understanding AMD NPT in xen

[Steven <wangwangkang@xxxxxxxxx>]

This clarifies everything. Thanks.

- Hui

On Thu, Apr 12, 2012 at 5:50 PM, Huang2, Wei <Wei.Huang2@xxxxxxx> wrote:
> Reformat:
>
> 1. To find out gPML4E
> * Traverse nested page table using gCR3 to locate guest level-4 page (PML4 
> table)
> * Use PML4 offset (bit 47:39) to get the value of gPML4E
>
> 2. To find out gPDPE
> * Traverse nested page table using gPML4E to locate guest level-3 page (PDP 
> table)
> * Use PDP offset (bit 38:30) to get the value of gPDPE
>
> 3. To find out gPDE
> * Traverse nested page table using gPDPE to locate guest level-2 page (PD 
> table)
> * Use PD offset (bit 29:21) to get the value of gPDE
>
> 4. To find out gPTE
> * Traverse nested page table using gPDE to locate guest level-1 page (PT 
> table)
> * Use PT offset (bit 20:12) to get the value of gPTE
>
> 5. To find out gData
> * Traverse nested page table using gPTE to locate guest data page
> * Use physical page offset (bit 11:0) to get the data value
>
>
> -----Original Message-----
> From: xen-devel-bounces@xxxxxxxxxxxxx 
> [mailto:xen-devel-bounces@xxxxxxxxxxxxx] On Behalf Of Huang2, Wei
> Sent: Thursday, April 12, 2012 4:35 PM
> To: Steven; Wang2, Wei; xen-devel@xxxxxxxxxxxxxxxxxxx
> Subject: Re: [Xen-devel] Understanding AMD NPT in xen
>
> White page info is more accurate. The slides was a bit vague. Here are the 
> steps, assuming that CPU doesn't have TLB:
>
> 1. To find out gPML4E
> * Traverse nested page table using gCR3 to locate guest level-4 page (PML4 
> table)
> * Use PML4 offset (bit 47:39) to get the value of gPML4E
> 2. To find out gPDPE
> * Traverse nested page table using gPML4E to locate guest level-3 page (PDP 
> table)
> * Use PDP offset (bit 38:30) to get the value of gPDPE
> 3. To find out gPDE
> * Traverse nested page table using gPDPE to locate guest level-2 page (PD 
> table)
> * Use PD offset (bit 29:21) to get the value of gPDE
> 4. To find out gPTE
> * Traverse nested page table using gPDE to locate guest level-1 page (PT 
> table)
> * Use PT offset (bit 20:12) to get the value of gPTE
> 5. To find out gData
> * Traverse nested page table using gPTE to locate guest data page
> * Use physical page offset (bit 11:0) to get the data value
>
> TLB will accelerate this walking significantly.
>
> -Wei
>
> -----Original Message-----
> From: xen-devel-bounces@xxxxxxxxxxxxx 
> [mailto:xen-devel-bounces@xxxxxxxxxxxxx] On Behalf Of Steven
> Sent: Thursday, April 12, 2012 12:06 PM
> To: Wang2, Wei; xen-devel@xxxxxxxxxxxxxxxxxxx
> Subject: [Xen-devel] Understanding AMD NPT in xen
>
> Hi, Wei,
> I have read you slides in xen summit 2007 about NPT in AMD, "AMD
> Barcelona and Nested Paging Support in Xen".
> However, I have some question regarding the nested page walk in your slide 8.
>
> In your slide 8, the first step is to get gPA from get_PML4(gCR3,gVA).
> I assume that it use the [47:39] bit of gVA.
> However, in another AMD white paper, "AMD-VTM Nested Paging".
> http://developer.amd.com/assets/NPT-WP-1%201-final-TM.pdf
> In its figure 4, I saw that the first step is to translate gCR3 using
> nested page walk and then combine with the gVA[47:39] to read the
> table entry.
>
> These two documents look having different order of reading the guest
> page table. In the slides, it first get_PML4. But in the white paper,
> it first does nested page walk.
> I am wondering which one is true. Thanks.
>
> - ha
>
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