# HG changeset patch
# User Wei Huang <wei.huang2@xxxxxxx>
# Date 1333061831 18000
# Node ID 07f17f70ffe4e733eff1965e011be5693622d129
# Parent  d7fdc948f6540427c4c20da216b304fc7a11cd76
AMD_LWP: add interrupt support for AMD LWP

This patch adds interrupt support for AMD lightweight profiling. It
registers interrupt handler using CPU affiliated interrupt delegate.
Hypervisor reinjects virtual interrupt into guest VM using local APIC.

Signed-off-by: Wei Huang <wei.huang2@xxxxxxx>

diff -r d7fdc948f654 -r 07f17f70ffe4 xen/arch/x86/hvm/svm/svm.c
--- a/xen/arch/x86/hvm/svm/svm.c	Thu Mar 29 17:51:16 2012 -0500
+++ b/xen/arch/x86/hvm/svm/svm.c	Thu Mar 29 17:57:11 2012 -0500
@@ -759,7 +759,17 @@
 {
     /* Only LWP_CFG is reloaded. LWP_CBADDR will be reloaded via xrstor. */
    if ( v->arch.hvm_svm.guest_lwp_cfg ) 
-       wrmsrl(MSR_AMD64_LWP_CFG, v->arch.hvm_svm.guest_lwp_cfg);
+       wrmsrl(MSR_AMD64_LWP_CFG, v->arch.hvm_svm.cpu_lwp_cfg);
+}
+
+int svm_lwp_intr_handler(struct cpu_user_regs *regs)
+{
+    struct vcpu *v = current;
+
+    vlapic_set_irq(vcpu_vlapic(v), 
+                   (v->arch.hvm_svm.guest_lwp_cfg >> 40) && 0xff, 0);
+
+    return 1;
 }
 
 /* Update LWP_CFG MSR (0xc0000105). Return -1 if error; otherwise returns 0. */
@@ -776,12 +786,24 @@
         /* generate #GP if guest tries to turn on unsupported features. */
         if ( msr_low & ~edx)
             return -1;
-        
-        wrmsrl(MSR_AMD64_LWP_CFG, msr_content);
-        /* CPU might automatically correct reserved bits. So read it back. */
-        rdmsrl(MSR_AMD64_LWP_CFG, msr_content);
+
         v->arch.hvm_svm.guest_lwp_cfg = msr_content;
 
+        /* setup interrupt handler */
+        if ( (msr_content & 0x80000000) && ((msr_content >> 40) & 0xff) )
+        {
+            v->arch.hvm_svm.cpu_lwp_cfg = (msr_content & 0xffff00ffffffffffULL)
+                | ((uint64_t)CPU_AFFILIATE_VECTOR << 40);
+            v->arch.hvm_vcpu.affiliate_intr_handler = svm_lwp_intr_handler;
+        }
+        else
+        {
+            /* disable interrupt */
+            v->arch.hvm_svm.cpu_lwp_cfg = msr_content & 0xffff00ff7fffffffULL;
+            v->arch.hvm_vcpu.affiliate_intr_handler = NULL;
+        }
+        wrmsrl(MSR_AMD64_LWP_CFG, v->arch.hvm_svm.cpu_lwp_cfg);
+
         /* track nonalzy state if LWP_CFG is non-zero. */
         v->arch.nonlazy_xstate_used = !!(msr_content);
     }
diff -r d7fdc948f654 -r 07f17f70ffe4 xen/include/asm-x86/hvm/svm/vmcb.h
--- a/xen/include/asm-x86/hvm/svm/vmcb.h	Thu Mar 29 17:51:16 2012 -0500
+++ b/xen/include/asm-x86/hvm/svm/vmcb.h	Thu Mar 29 17:57:11 2012 -0500
@@ -515,7 +515,8 @@
     uint64_t guest_sysenter_eip;
     
     /* AMD lightweight profiling MSR */
-    uint64_t guest_lwp_cfg;
+    uint64_t guest_lwp_cfg;       /* guest version */
+    uint64_t cpu_lwp_cfg;          /* cpu version */
 
     /* OSVW MSRs */
     struct {