Re: [Xen-devel] [PATCH 0 of 2] Support for Paging/Sharing on AMD

["Andres Lagar-Cavilla" <andres@xxxxxxxxxxxxxxxx>]

> At 07:46 -0700 on 29 Mar (1333007195), Andres Lagar-Cavilla wrote:
>> > At 11:43 -0400 on 27 Mar (1332848606), Andres Lagar-Cavilla wrote:
>> >> This is a partial repost of the series first sent on Mar 22nd.
>> >>
>> >> It currently contains two patches
>> >> - Teach paging types to p2m-pt.
>> >> - Add interlock for iommu and mem paging/sharing.
>> >>
>> >> The first patch is rebased to apply on top of
>> >> http://lists.xen.org/archives/html/xen-devel/2012-03/msg01982.html
>> >> and addresses some feedbackfrom Tim Deegan.
>> >>
>> >> The second patch prevents a passthrough device from being assigned to
>> a
>> >> domain
>> >> if mem paging or sharing have been turned on. And viceversa. This is
>> a
>> >> missing
>> >> check that is necessary for both Intel and AMD processors.
>> >>
>> >> Signed-off-by: Andres Lagar-Cavilla <andres@xxxxxxxxxxxxxxxx>
>> >
>> > Applied, thanks.
>>
>> Great, thanks.
>>
>> The question now is what to do for AMD+paging in Xen 4.2. It works
>> partially, there are still VMEXIT_shutdown hvm crashes happening with pv
>> drivers.
>>
>> I see two options
>> - leave as is, disabled
>> - enable it and tag it experimental (printk, documentation, etc)
>
> I'm happy to mark it 'experimental' and put appropriate words in the
> release notes about the PV driver problem.

Patch below. Not sure about where to place more detailed documentation
Andres

# HG changeset patch
# User Andres Lagar-Cavilla <andres@xxxxxxxxxxxxxxxx>
# Date 1333034738 14400
# Node ID 228f7aebb0ff1691cf7885866e1b2ae92f1649f7
# Parent  5a7e18e57c7260141b07d037c37504bcce862d74
x86/mm: Enable paging and sharing in AMD NPT mode -- *experimental*.

Both features are mutually exclusive with sharing iommu and p2m tables. Still
not bug-free, considered experimental.

Signed-off-by: Andres Lagar-Cavilla <andres@xxxxxxxxxxxxxxxx>
Signed-off-by: Adin Scannell <adin@xxxxxxxxxxx>

diff -r 5a7e18e57c72 -r 228f7aebb0ff xen/arch/x86/mm/mem_event.c
--- a/xen/arch/x86/mm/mem_event.c
+++ b/xen/arch/x86/mm/mem_event.c
@@ -563,8 +563,11 @@ int mem_event_domctl(struct domain *d, x
             if ( !hap_enabled(d) )
                 break;

-            /* Currently only EPT is supported */
-            if ( boot_cpu_data.x86_vendor != X86_VENDOR_INTEL )
+            /* Currently EPT or AMD with no iommu/hap page table sharing are
+             * supported. Further, AMD considered experimental atm. */
+            if ( !((boot_cpu_data.x86_vendor == X86_VENDOR_INTEL) ||
+                   ((boot_cpu_data.x86_vendor == X86_VENDOR_AMD) &&
+                     !iommu_use_hap_pt(d))) )
                 break;

             /* No paging if iommu is used */
diff -r 5a7e18e57c72 -r 228f7aebb0ff xen/arch/x86/mm/mem_sharing.c
--- a/xen/arch/x86/mm/mem_sharing.c
+++ b/xen/arch/x86/mm/mem_sharing.c
@@ -1201,6 +1201,13 @@ int mem_sharing_domctl(struct domain *d,
     if ( !hap_enabled(d) )
          return -ENODEV;

+    /* Currently EPT or AMD with no iommu/hap page table sharing are
+     * supported. Further, AMD considered experimental atm. */
+    if ( !((boot_cpu_data.x86_vendor == X86_VENDOR_INTEL) ||
+           ((boot_cpu_data.x86_vendor == X86_VENDOR_AMD) &&
+             !iommu_use_hap_pt(d))) )
+        return -ENODEV;
+
     switch(mec->op)
     {
         case XEN_DOMCTL_MEM_SHARING_CONTROL:

>
> Tim.
>



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