Re: [Xen-devel] [PATCH 03 of 11] arm: More SMP bringup

[Ian Campbell <Ian.Campbell@xxxxxxxxxx>]

On Fri, 2012-03-09 at 16:47 +0000, Tim Deegan wrote:

> +     /* Non-boot CPUs report that they've got this far */
> +     ldr   r0, =ready_cpus
> +1:   ldrex r1, [r0]               /*            { read # of ready CPUs } */
> +     add   r1, r1, #1             /* Atomically { ++                   } */
> +     strex r2, r1, [r0]           /*            { writeback            } */
> +     teq   r2, #0
> +     bne   1b
> +     dsb
> +
> +     /* Here, the non-boot CPUs must wait again -- they're now running on
> +      * the boot CPU's pagetables so it's safe for the boot CPU to
> +      * overwrite the non-relocated copy of Xen.  Once it's done that,
> +      * and brought up the memory allocator, non-boot CPUs can get their
> +      * own stacks and enter C. */
> +1:   wfe
> +     b 1b
> +
> +launch:      
>       ldr   sp, =init_stack        /* Supply a stack */

This really confused me until I realised that the event to push a
non-boot CPU out of that wfe loop would never come at this point in the
series!

If I boot on a 4 way AEM model then my dom0 kernel hangs at "Calibrating
delay loop". However I don't see this booting with this series on a 1
way model so I don't consider it a regression (yet).

I also get:
        At 0x00000000, Error: Exclusive Access Into non-Normal memory
        Access at VA = 0x80260014, TLB Entry = 
        CoreNum:0, Virtual base = 0x0, Physical base = 0x0, size = 0x0, 
tlb_index = 0x0
            Global, ipa_base = 0x0000000000000000, Strongly 
Ordered/Device-nGnRnE outer-shareable AP = 011, domain = 10
            Inner NonCacheable, Outer NonCacheable
            Pagetable entry l1 = 0x00000000
But I'm assuming this is the model being confused by the use of
ldr/strex before enabling paging (although it would be worth checking
that those instr aren't dependent on paging in some way?).

Anyway... I've committed all 11 patches in this series. Thanks!

Ian.


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