[Date Prev][Date Next][Thread Prev][Thread Next][Date Index][Thread Index] [Xen-devel] [Patch] X86: expose HLE/RTM features to dom0
X86: expose HLE/RTM features to dom0 Intel recently release 2 new features, HLE and TRM. Refer to http://software.intel.com/file/41417. This patch expose them to dom0. Signed-off-by: Liu, Jinsong <jinsong.liu@xxxxxxxxx> diff -r 92e03310878f xen/arch/x86/traps.c --- a/xen/arch/x86/traps.c Wed Feb 08 21:05:52 2012 +0800 +++ b/xen/arch/x86/traps.c Mon Feb 27 02:23:42 2012 +0800 @@ -857,9 +857,11 @@ case 0x00000007: if ( regs->ecx == 0 ) b &= (cpufeat_mask(X86_FEATURE_BMI1) | + cpufeat_mask(X86_FEATURE_HLE) | cpufeat_mask(X86_FEATURE_AVX2) | cpufeat_mask(X86_FEATURE_BMI2) | cpufeat_mask(X86_FEATURE_ERMS) | + cpufeat_mask(X86_FEATURE_RTM) | cpufeat_mask(X86_FEATURE_FSGSBASE)); else b = 0; diff -r 92e03310878f xen/include/asm-x86/cpufeature.h --- a/xen/include/asm-x86/cpufeature.h Wed Feb 08 21:05:52 2012 +0800 +++ b/xen/include/asm-x86/cpufeature.h Mon Feb 27 02:23:42 2012 +0800 @@ -149,11 +149,13 @@ /* Intel-defined CPU features, CPUID level 0x00000007:0 (ebx), word 7 */ #define X86_FEATURE_FSGSBASE (7*32+ 0) /* {RD,WR}{FS,GS}BASE instructions */ #define X86_FEATURE_BMI1 (7*32+ 3) /* 1st bit manipulation extensions */ +#define X86_FEATURE_HLE (7*32+ 4) /* Hardware Lock Elision */ #define X86_FEATURE_AVX2 (7*32+ 5) /* AVX2 instructions */ #define X86_FEATURE_SMEP (7*32+ 7) /* Supervisor Mode Execution Protection */ #define X86_FEATURE_BMI2 (7*32+ 8) /* 2nd bit manipulation extensions */ #define X86_FEATURE_ERMS (7*32+ 9) /* Enhanced REP MOVSB/STOSB */ #define X86_FEATURE_INVPCID (7*32+10) /* Invalidate Process Context ID */ +#define X86_FEATURE_RTM (7*32+11) /* Restricted Transactional Memory */ #define cpu_has(c, bit) test_bit(bit, (c)->x86_capability) #define boot_cpu_has(bit) test_bit(bit, boot_cpu_data.x86_capability) Attachment:
expose_hlertm_for_dom0.patch _______________________________________________ Xen-devel mailing list Xen-devel@xxxxxxxxxxxxx http://lists.xen.org/xen-devel
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