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[Xen-devel] [PATCH 1/2] x86/vMCE: don't advertise features we don't support

... or even know of. Apart from CMCI, which was masked off already,
this now also suppresses the advertising of extended state registers
(reading of which would likely be meaningless in a guest and represent
an information leak).

Signed-off-by: Jan Beulich <jbeulich@xxxxxxxx>

--- a/xen/arch/x86/cpu/mcheck/vmce.c
+++ b/xen/arch/x86/cpu/mcheck/vmce.c
@@ -457,7 +457,7 @@ int vmce_init(struct cpuinfo_x86 *c)
     rdmsrl(MSR_IA32_MCG_CAP, value);
     /* For Guest vMCE usage */
-    g_mcg_cap = value & ~MCG_CMCI_P;
+    g_mcg_cap = value & (MCG_CAP_COUNT | MCG_CTL_P | MCG_TES_P | MCG_SER_P);
     if (value & MCG_CTL_P)
         rdmsrl(MSR_IA32_MCG_CTL, h_mcg_ctl);
--- a/xen/arch/x86/cpu/mcheck/x86_mca.h
+++ b/xen/arch/x86/cpu/mcheck/x86_mca.h
@@ -30,12 +30,13 @@
 /* Bitfield of the MSR_IA32_MCG_CAP register */
-#define MCG_SER_P               (1UL<<24)
 #define MCG_CAP_COUNT           0x00000000000000ffULL
-#define MCG_CTL_P               0x0000000000000100ULL
-#define MCG_EXT_P              (1UL<<9)
-#define MCG_EXT_CNT            (16)
-#define MCG_CMCI_P             (1UL<<10)
+#define MCG_CTL_P               (1ULL<<8)
+#define MCG_EXT_P               (1ULL<<9)
+#define MCG_CMCI_P              (1ULL<<10)
+#define MCG_TES_P               (1ULL<<11)
+#define MCG_EXT_CNT             16
+#define MCG_SER_P               (1ULL<<24)
 /* Other bits are reserved */
 /* Bitfield of the MSR_IA32_MCG_STATUS register */

Attachment: x86-vmce-mcg_ctl-default.patch
Description: Text document

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