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[Date Prev][Date Next][Thread Prev][Thread Next][Date Index][Thread Index] Re: [Xen-devel] [PATCH V6 10/11] Introduce Xen PCI Passthrough, MSI (3/3)
>>> On 13.02.12 at 13:20, Anthony PERARD <anthony.perard@xxxxxxxxxx> wrote: > From: Jiang Yunhong <yunhong.jiang@xxxxxxxxx> > > A more complete history can be found here: > git://xenbits.xensource.com/qemu-xen-unstable.git This needs to be updated to include the changes in http://xenbits.xen.org/gitweb/?p=qemu-xen-unstable.git;a=commitdiff;h=bb36d632e4cabf47882adff07a45c6702c4a5b30 (and hopefully the broken function that got fixed in http://xenbits.xen.org/gitweb/?p=qemu-xen-unstable.git;a=commitdiff;h=8cc8a3651c9c5bc2d0086d12f4b870fc525b9387 didn't even make it into this patch set). In particular it must be avoided to map the MSI-X table with PROT_WRITE, and the respective MMIO range should not get assigned to the guest at all. Jan > Signed-off-by: Jiang Yunhong <yunhong.jiang@xxxxxxxxx> > Signed-off-by: Shan Haitao <haitao.shan@xxxxxxxxx> > Signed-off-by: Anthony PERARD <anthony.perard@xxxxxxxxxx> > --- > Makefile.target | 1 + > hw/apic-msidef.h | 2 + > hw/xen_pci_passthrough.c | 32 ++ > hw/xen_pci_passthrough.h | 48 +++ > hw/xen_pci_passthrough_config_init.c | 480 ++++++++++++++++++++++++ > hw/xen_pci_passthrough_msi.c | 667 > ++++++++++++++++++++++++++++++++++ > 6 files changed, 1230 insertions(+), 0 deletions(-) > create mode 100644 hw/xen_pci_passthrough_msi.c > > diff --git a/Makefile.target b/Makefile.target > index 8fc2ca3..3517cab 100644 > --- a/Makefile.target > +++ b/Makefile.target > @@ -220,6 +220,7 @@ obj-i386-$(CONFIG_XEN) += xen_platform.o > obj-i386-$(CONFIG_XEN_PCI_PASSTHROUGH) += host-pci-device.o > obj-i386-$(CONFIG_XEN_PCI_PASSTHROUGH) += xen_pci_passthrough.o > obj-i386-$(CONFIG_XEN_PCI_PASSTHROUGH) += xen_pci_passthrough_config_init.o > +obj-i386-$(CONFIG_XEN_PCI_PASSTHROUGH) += xen_pci_passthrough_msi.o > > # Inter-VM PCI shared memory > CONFIG_IVSHMEM = > diff --git a/hw/apic-msidef.h b/hw/apic-msidef.h > index 3182f0b..6e2eb71 100644 > --- a/hw/apic-msidef.h > +++ b/hw/apic-msidef.h > @@ -22,6 +22,8 @@ > > #define MSI_ADDR_DEST_MODE_SHIFT 2 > > +#define MSI_ADDR_REDIRECTION_SHIFT 3 > + > #define MSI_ADDR_DEST_ID_SHIFT 12 > #define MSI_ADDR_DEST_ID_MASK 0x00ffff0 > > diff --git a/hw/xen_pci_passthrough.c b/hw/xen_pci_passthrough.c > index bdc3690..1257ce2 100644 > --- a/hw/xen_pci_passthrough.c > +++ b/hw/xen_pci_passthrough.c > @@ -36,6 +36,20 @@ > * > * Write '1' > * - Set real bit to '1'. > + * > + * MSI interrupt: > + * Initialize MSI register(pt_msi_setup, pt_msi_update) > + * Bind MSI(xc_domain_update_msi_irq) > + * <fail> > + * - Unmap MSI. > + * - Set dev->msi->pirq to '-1'. > + * > + * MSI-X interrupt: > + * Initialize MSI-X register(pt_msix_update_one) > + * Bind MSI-X(xc_domain_update_msi_irq) > + * <fail> > + * - Unmap MSI-X. > + * - Set entry->pirq to '-1'. > */ > > #include <sys/ioctl.h> > @@ -362,6 +376,7 @@ static void pt_iomem_map(XenPCIPassthroughState *s, int > i, > } > > if (!first_map && old_ebase != PT_PCI_BAR_UNMAPPED) { > + pt_add_msix_mapping(s, i); > /* Remove old mapping */ > rc = xc_domain_memory_mapping(xen_xc, xen_domid, > old_ebase >> XC_PAGE_SHIFT, > @@ -386,6 +401,16 @@ static void pt_iomem_map(XenPCIPassthroughState *s, int > i, > if (rc) { > PT_ERR(&s->dev, "create new mapping failed! (rc: %i)\n", rc); > } > + > + rc = pt_remove_msix_mapping(s, i); > + if (rc != 0) { > + PT_ERR(&s->dev, "Remove MSI-X MMIO mapping failed! (rc: %d)\n", > + rc); > + } > + > + if (old_ebase != e_phys && old_ebase != -1) { > + pt_msix_update_remap(s, i); > + } > } > } > > @@ -766,6 +791,13 @@ static int pt_unregister_device(PCIDevice *d) > } > } > > + if (s->msi) { > + pt_msi_disable(s); > + } > + if (s->msix) { > + pt_msix_disable(s); > + } > + > if (machine_irq) { > mapped_machine_irq[machine_irq]--; > > diff --git a/hw/xen_pci_passthrough.h b/hw/xen_pci_passthrough.h > index 0b9902d..deeba89 100644 > --- a/hw/xen_pci_passthrough.h > +++ b/hw/xen_pci_passthrough.h > @@ -174,6 +174,37 @@ typedef struct XenPTRegGroup { > > > #define PT_UNASSIGNED_PIRQ (-1) > +typedef struct XenPTMSI { > + uint16_t flags; > + uint32_t addr_lo; /* guest message address */ > + uint32_t addr_hi; /* guest message upper address */ > + uint16_t data; /* guest message data */ > + uint32_t ctrl_offset; /* saved control offset */ > + int pirq; /* guest pirq corresponding */ > + bool initialized; /* when guest MSI is initialized */ > + bool mapped; /* when pirq is mapped */ > +} XenPTMSI; > + > +typedef struct XenPTMSIXEntry { > + int pirq; > + uint64_t addr; > + uint32_t data; > + uint32_t vector_ctrl; > + bool updated; /* indicate whether MSI ADDR or DATA is updated */ > +} XenPTMSIXEntry; > +typedef struct XenPTMSIX { > + uint32_t ctrl_offset; > + bool enabled; > + int total_entries; > + int bar_index; > + uint64_t table_base; > + uint32_t table_off; > + uint32_t table_offset_adjust; /* page align mmap */ > + uint64_t mmio_base_addr; > + MemoryRegion mmio; > + void *phys_iomem_base; > + XenPTMSIXEntry msix_entry[0]; > +} XenPTMSIX; > > struct XenPCIPassthroughState { > PCIDevice dev; > @@ -186,6 +217,9 @@ struct XenPCIPassthroughState { > > uint32_t machine_irq; > > + XenPTMSI *msi; > + XenPTMSIX *msix; > + > MemoryRegion bar[PCI_NUM_REGIONS - 1]; > MemoryRegion rom; > }; > @@ -262,4 +296,18 @@ static inline uint8_t pci_intx(XenPCIPassthroughState > *s) > return r_val; > } > > +/* MSI/MSI-X */ > +int pt_msi_set_enable(XenPCIPassthroughState *s, bool en); > +int pt_msi_setup(XenPCIPassthroughState *s); > +int pt_msi_update(XenPCIPassthroughState *d); > +void pt_msi_disable(XenPCIPassthroughState *s); > + > +int pt_msix_init(XenPCIPassthroughState *s, uint32_t base); > +void pt_msix_delete(XenPCIPassthroughState *s); > +int pt_msix_update(XenPCIPassthroughState *s); > +int pt_msix_update_remap(XenPCIPassthroughState *s, int bar_index); > +void pt_msix_disable(XenPCIPassthroughState *s); > +int pt_add_msix_mapping(XenPCIPassthroughState *s, int bar_index); > +int pt_remove_msix_mapping(XenPCIPassthroughState *s, int bar_index); > + > #endif /* !QEMU_HW_XEN_PCI_PASSTHROUGH_H */ > diff --git a/hw/xen_pci_passthrough_config_init.c > b/hw/xen_pci_passthrough_config_init.c > index 2fb27ff..430c26a 100644 > --- a/hw/xen_pci_passthrough_config_init.c > +++ b/hw/xen_pci_passthrough_config_init.c > @@ -1125,6 +1125,419 @@ static XenPTRegInfo pt_emu_reg_pcie_tbl[] = { > }; > > > +/******************************** > + * MSI Capability > + */ > + > +/* Helper */ > +static bool pt_msgdata_check_type(uint32_t offset, uint16_t flags) > +{ > + /* check the offset whether matches the type or not */ > + bool is_32 = (offset == PCI_MSI_DATA_32) && !(flags & > PCI_MSI_FLAGS_64BIT); > + bool is_64 = (offset == PCI_MSI_DATA_64) && (flags & > PCI_MSI_FLAGS_64BIT); > + return is_32 || is_64; > +} > + > +/* Message Control register */ > +static int pt_msgctrl_reg_init(XenPCIPassthroughState *s, > + XenPTRegInfo *reg, uint32_t real_offset, > + uint32_t *data) > +{ > + PCIDevice *d = &s->dev; > + XenPTMSI *msi = s->msi; > + uint16_t reg_field = 0; > + > + /* use I/O device register's value as initial value */ > + reg_field = pci_get_word(d->config + real_offset); > + > + if (reg_field & PCI_MSI_FLAGS_ENABLE) { > + PT_LOG(&s->dev, "MSI already enabled, disabling it first\n"); > + host_pci_set_word(s->real_device, real_offset, > + reg_field & ~PCI_MSI_FLAGS_ENABLE); > + } > + msi->flags |= reg_field; > + msi->ctrl_offset = real_offset; > + msi->initialized = false; > + msi->mapped = false; > + > + *data = reg->init_val; > + return 0; > +} > +static int pt_msgctrl_reg_write(XenPCIPassthroughState *s, XenPTReg > *cfg_entry, > + uint16_t *value, uint16_t dev_value, > + uint16_t valid_mask) > +{ > + XenPTRegInfo *reg = cfg_entry->reg; > + XenPTMSI *msi = s->msi; > + uint16_t writable_mask = 0; > + uint16_t throughable_mask = 0; > + uint16_t val; > + > + /* Currently no support for multi-vector */ > + if (*value & PCI_MSI_FLAGS_QSIZE) { > + PT_WARN(&s->dev, "Tries to set more than 1 vector ctrl %x\n", > *value); > + } > + > + /* modify emulate register */ > + writable_mask = reg->emu_mask & ~reg->ro_mask & valid_mask; > + cfg_entry->data = PT_MERGE_VALUE(*value, cfg_entry->data, writable_mask); > + msi->flags |= cfg_entry->data & ~PCI_MSI_FLAGS_ENABLE; > + > + /* create value for writing to I/O device register */ > + val = *value; > + throughable_mask = ~reg->emu_mask & valid_mask; > + *value = PT_MERGE_VALUE(*value, dev_value, throughable_mask); > + > + /* update MSI */ > + if (val & PCI_MSI_FLAGS_ENABLE) { > + /* setup MSI pirq for the first time */ > + if (!msi->initialized) { > + /* Init physical one */ > + PT_LOG(&s->dev, "setup MSI\n"); > + if (pt_msi_setup(s)) { > + /* We do not broadcast the error to the framework code, so > + * that MSI errors are contained in MSI emulation code and > + * QEMU can go on running. > + * Guest MSI would be actually not working. > + */ > + *value &= ~PCI_MSI_FLAGS_ENABLE; > + PT_WARN(&s->dev, "Can not map MSI.\n"); > + return 0; > + } > + if (pt_msi_update(s)) { > + *value &= ~PCI_MSI_FLAGS_ENABLE; > + PT_WARN(&s->dev, "Can not bind MSI\n"); > + return 0; > + } > + msi->initialized = true; > + msi->mapped = true; > + } > + msi->flags |= PCI_MSI_FLAGS_ENABLE; > + } else { > + msi->flags &= ~PCI_MSI_FLAGS_ENABLE; > + } > + > + /* pass through MSI_ENABLE bit */ > + *value &= ~PCI_MSI_FLAGS_ENABLE; > + *value |= val & PCI_MSI_FLAGS_ENABLE; > + > + return 0; > +} > + > +/* initialize Message Upper Address register */ > +static int pt_msgaddr64_reg_init(XenPCIPassthroughState *s, > + XenPTRegInfo *reg, uint32_t real_offset, > + uint32_t *data) > +{ > + /* no need to initialize in case of 32 bit type */ > + if (!(s->msi->flags & PCI_MSI_FLAGS_64BIT)) { > + *data = PT_INVALID_REG; > + } else { > + *data = reg->init_val; > + } > + > + return 0; > +} > +/* this function will be called twice (for 32 bit and 64 bit type) */ > +/* initialize Message Data register */ > +static int pt_msgdata_reg_init(XenPCIPassthroughState *s, > + XenPTRegInfo *reg, uint32_t real_offset, > + uint32_t *data) > +{ > + uint32_t flags = s->msi->flags; > + uint32_t offset = reg->offset; > + > + /* check the offset whether matches the type or not */ > + if (pt_msgdata_check_type(offset, flags)) { > + *data = reg->init_val; > + } else { > + *data = PT_INVALID_REG; > + } > + return 0; > +} > + > +/* write Message Address register */ > +static int pt_msgaddr32_reg_write(XenPCIPassthroughState *s, > + XenPTReg *cfg_entry, uint32_t *value, > + uint32_t dev_value, uint32_t valid_mask) > +{ > + XenPTRegInfo *reg = cfg_entry->reg; > + uint32_t writable_mask = 0; > + uint32_t throughable_mask = 0; > + uint32_t old_addr = cfg_entry->data; > + > + /* modify emulate register */ > + writable_mask = reg->emu_mask & ~reg->ro_mask & valid_mask; > + cfg_entry->data = PT_MERGE_VALUE(*value, cfg_entry->data, writable_mask); > + s->msi->addr_lo = cfg_entry->data; > + > + /* create value for writing to I/O device register */ > + throughable_mask = ~reg->emu_mask & valid_mask; > + *value = PT_MERGE_VALUE(*value, dev_value, throughable_mask); > + > + /* update MSI */ > + if (cfg_entry->data != old_addr) { > + if (s->msi->mapped) { > + pt_msi_update(s); > + } > + } > + > + return 0; > +} > +/* write Message Upper Address register */ > +static int pt_msgaddr64_reg_write(XenPCIPassthroughState *s, > + XenPTReg *cfg_entry, uint32_t *value, > + uint32_t dev_value, uint32_t valid_mask) > +{ > + XenPTRegInfo *reg = cfg_entry->reg; > + uint32_t writable_mask = 0; > + uint32_t throughable_mask = 0; > + uint32_t old_addr = cfg_entry->data; > + > + /* check whether the type is 64 bit or not */ > + if (!(s->msi->flags & PCI_MSI_FLAGS_64BIT)) { > + PT_ERR(&s->dev, > + "Can't write to the upper address without 64 bit > support\n"); > + return -1; > + } > + > + /* modify emulate register */ > + writable_mask = reg->emu_mask & ~reg->ro_mask & valid_mask; > + cfg_entry->data = PT_MERGE_VALUE(*value, cfg_entry->data, writable_mask); > + /* update the msi_info too */ > + s->msi->addr_hi = cfg_entry->data; > + > + /* create value for writing to I/O device register */ > + throughable_mask = ~reg->emu_mask & valid_mask; > + *value = PT_MERGE_VALUE(*value, dev_value, throughable_mask); > + > + /* update MSI */ > + if (cfg_entry->data != old_addr) { > + if (s->msi->mapped) { > + pt_msi_update(s); > + } > + } > + > + return 0; > +} > + > + > +/* this function will be called twice (for 32 bit and 64 bit type) */ > +/* write Message Data register */ > +static int pt_msgdata_reg_write(XenPCIPassthroughState *s, XenPTReg > *cfg_entry, > + uint16_t *value, uint16_t dev_value, > + uint16_t valid_mask) > +{ > + XenPTRegInfo *reg = cfg_entry->reg; > + XenPTMSI *msi = s->msi; > + uint16_t writable_mask = 0; > + uint16_t throughable_mask = 0; > + uint16_t old_data = cfg_entry->data; > + uint32_t offset = reg->offset; > + > + /* check the offset whether matches the type or not */ > + if (!pt_msgdata_check_type(offset, msi->flags)) { > + /* exit I/O emulator */ > + PT_ERR(&s->dev, "the offset does not match the 32/64 bit type!\n"); > + return -1; > + } > + > + /* modify emulate register */ > + writable_mask = reg->emu_mask & ~reg->ro_mask & valid_mask; > + cfg_entry->data = PT_MERGE_VALUE(*value, cfg_entry->data, writable_mask); > + /* update the msi_info too */ > + msi->data = cfg_entry->data; > + > + /* create value for writing to I/O device register */ > + throughable_mask = ~reg->emu_mask & valid_mask; > + *value = PT_MERGE_VALUE(*value, dev_value, throughable_mask); > + > + /* update MSI */ > + if (cfg_entry->data != old_data) { > + if (msi->mapped) { > + pt_msi_update(s); > + } > + } > + > + return 0; > +} > + > +/* MSI Capability Structure reg static infomation table */ > +static XenPTRegInfo pt_emu_reg_msi_tbl[] = { > + /* Next Pointer reg */ > + { > + .offset = PCI_CAP_LIST_NEXT, > + .size = 1, > + .init_val = 0x00, > + .ro_mask = 0xFF, > + .emu_mask = 0xFF, > + .init = pt_ptr_reg_init, > + .u.b.read = pt_byte_reg_read, > + .u.b.write = pt_byte_reg_write, > + .u.b.restore = NULL, > + }, > + /* Message Control reg */ > + { > + .offset = PCI_MSI_FLAGS, > + .size = 2, > + .init_val = 0x0000, > + .ro_mask = 0xFF8E, > + .emu_mask = 0x007F, > + .init = pt_msgctrl_reg_init, > + .u.w.read = pt_word_reg_read, > + .u.w.write = pt_msgctrl_reg_write, > + .u.w.restore = NULL, > + }, > + /* Message Address reg */ > + { > + .offset = PCI_MSI_ADDRESS_LO, > + .size = 4, > + .init_val = 0x00000000, > + .ro_mask = 0x00000003, > + .emu_mask = 0xFFFFFFFF, > + .no_wb = 1, > + .init = pt_common_reg_init, > + .u.dw.read = pt_long_reg_read, > + .u.dw.write = pt_msgaddr32_reg_write, > + .u.dw.restore = NULL, > + }, > + /* Message Upper Address reg (if PCI_MSI_FLAGS_64BIT set) */ > + { > + .offset = PCI_MSI_ADDRESS_HI, > + .size = 4, > + .init_val = 0x00000000, > + .ro_mask = 0x00000000, > + .emu_mask = 0xFFFFFFFF, > + .no_wb = 1, > + .init = pt_msgaddr64_reg_init, > + .u.dw.read = pt_long_reg_read, > + .u.dw.write = pt_msgaddr64_reg_write, > + .u.dw.restore = NULL, > + }, > + /* Message Data reg (16 bits of data for 32-bit devices) */ > + { > + .offset = PCI_MSI_DATA_32, > + .size = 2, > + .init_val = 0x0000, > + .ro_mask = 0x0000, > + .emu_mask = 0xFFFF, > + .no_wb = 1, > + .init = pt_msgdata_reg_init, > + .u.w.read = pt_word_reg_read, > + .u.w.write = pt_msgdata_reg_write, > + .u.w.restore = NULL, > + }, > + /* Message Data reg (16 bits of data for 64-bit devices) */ > + { > + .offset = PCI_MSI_DATA_64, > + .size = 2, > + .init_val = 0x0000, > + .ro_mask = 0x0000, > + .emu_mask = 0xFFFF, > + .no_wb = 1, > + .init = pt_msgdata_reg_init, > + .u.w.read = pt_word_reg_read, > + .u.w.write = pt_msgdata_reg_write, > + .u.w.restore = NULL, > + }, > + { > + .size = 0, > + }, > +}; > + > + > +/************************************** > + * MSI-X Capability > + */ > + > +/* Message Control register for MSI-X */ > +static int pt_msixctrl_reg_init(XenPCIPassthroughState *s, > + XenPTRegInfo *reg, uint32_t real_offset, > + uint32_t *data) > +{ > + PCIDevice *d = &s->dev; > + uint16_t reg_field = 0; > + > + /* use I/O device register's value as initial value */ > + reg_field = pci_get_word(d->config + real_offset); > + > + if (reg_field & PCI_MSIX_FLAGS_ENABLE) { > + PT_LOG(d, "MSIX already enabled, disabling it first\n"); > + host_pci_set_word(s->real_device, real_offset, > + reg_field & ~PCI_MSIX_FLAGS_ENABLE); > + } > + > + s->msix->ctrl_offset = real_offset; > + > + *data = reg->init_val; > + return 0; > +} > +static int pt_msixctrl_reg_write(XenPCIPassthroughState *s, > + XenPTReg *cfg_entry, uint16_t *value, > + uint16_t dev_value, uint16_t valid_mask) > +{ > + XenPTRegInfo *reg = cfg_entry->reg; > + uint16_t writable_mask = 0; > + uint16_t throughable_mask = 0; > + > + int debug_msix_enabled_old; > + > + /* modify emulate register */ > + writable_mask = reg->emu_mask & ~reg->ro_mask & valid_mask; > + cfg_entry->data = PT_MERGE_VALUE(*value, cfg_entry->data, writable_mask); > + > + /* create value for writing to I/O device register */ > + throughable_mask = ~reg->emu_mask & valid_mask; > + *value = PT_MERGE_VALUE(*value, dev_value, throughable_mask); > + > + /* update MSI-X */ > + if ((*value & PCI_MSIX_FLAGS_ENABLE) > + && !(*value & PCI_MSIX_FLAGS_MASKALL)) { > + pt_msix_update(s); > + } > + > + debug_msix_enabled_old = s->msix->enabled; > + s->msix->enabled = !!(*value & PCI_MSIX_FLAGS_ENABLE); > + if (s->msix->enabled != debug_msix_enabled_old) { > + PT_LOG(&s->dev, "%s MSI-X\n", > + s->msix->enabled ? "enable" : "disable"); > + } > + > + return 0; > +} > + > +/* MSI-X Capability Structure reg static infomation table */ > +static XenPTRegInfo pt_emu_reg_msix_tbl[] = { > + /* Next Pointer reg */ > + { > + .offset = PCI_CAP_LIST_NEXT, > + .size = 1, > + .init_val = 0x00, > + .ro_mask = 0xFF, > + .emu_mask = 0xFF, > + .init = pt_ptr_reg_init, > + .u.b.read = pt_byte_reg_read, > + .u.b.write = pt_byte_reg_write, > + .u.b.restore = NULL, > + }, > + /* Message Control reg */ > + { > + .offset = PCI_MSI_FLAGS, > + .size = 2, > + .init_val = 0x0000, > + .ro_mask = 0x3FFF, > + .emu_mask = 0x0000, > + .init = pt_msixctrl_reg_init, > + .u.w.read = pt_word_reg_read, > + .u.w.write = pt_msixctrl_reg_write, > + .u.w.restore = NULL, > + }, > + { > + .size = 0, > + }, > +}; > + > + > /**************************** > * Capabilities > */ > @@ -1218,6 +1631,49 @@ static int pt_pcie_size_init(XenPCIPassthroughState > *s, > *size = pcie_size; > return 0; > } > +/* get MSI Capability Structure register group size */ > +static int pt_msi_size_init(XenPCIPassthroughState *s, > + const XenPTRegGroupInfo *grp_reg, > + uint32_t base_offset, uint8_t *size) > +{ > + PCIDevice *d = &s->dev; > + uint16_t msg_ctrl = 0; > + uint8_t msi_size = 0xa; > + > + msg_ctrl = pci_get_word(d->config + (base_offset + PCI_MSI_FLAGS)); > + > + /* check if 64-bit address is capable of per-vector masking */ > + if (msg_ctrl & PCI_MSI_FLAGS_64BIT) { > + msi_size += 4; > + } > + if (msg_ctrl & PCI_MSI_FLAGS_MASKBIT) { > + msi_size += 10; > + } > + > + s->msi = g_new0(XenPTMSI, 1); > + s->msi->pirq = PT_UNASSIGNED_PIRQ; > + > + *size = msi_size; > + return 0; > +} > +/* get MSI-X Capability Structure register group size */ > +static int pt_msix_size_init(XenPCIPassthroughState *s, > + const XenPTRegGroupInfo *grp_reg, > + uint32_t base_offset, uint8_t *size) > +{ > + int rc = 0; > + > + rc = pt_msix_init(s, base_offset); > + > + if (rc < 0) { > + PT_ERR(&s->dev, "Internal error: Invalid pt_msix_init.\n"); > + return rc; > + } > + > + *size = grp_reg->grp_size; > + return 0; > +} > + > > static const XenPTRegGroupInfo pt_emu_reg_grp_tbl[] = { > /* Header Type0 reg group */ > @@ -1250,6 +1706,14 @@ static const XenPTRegGroupInfo pt_emu_reg_grp_tbl[] = > { > .grp_size = 0x04, > .size_init = pt_reg_grp_size_init, > }, > + /* MSI Capability Structure reg group */ > + { > + .grp_id = PCI_CAP_ID_MSI, > + .grp_type = GRP_TYPE_EMU, > + .grp_size = 0xFF, > + .size_init = pt_msi_size_init, > + .emu_reg_tbl = pt_emu_reg_msi_tbl, > + }, > /* PCI-X Capabilities List Item reg group */ > { > .grp_id = PCI_CAP_ID_PCIX, > @@ -1294,6 +1758,14 @@ static const XenPTRegGroupInfo pt_emu_reg_grp_tbl[] = > { > .size_init = pt_pcie_size_init, > .emu_reg_tbl = pt_emu_reg_pcie_tbl, > }, > + /* MSI-X Capability Structure reg group */ > + { > + .grp_id = PCI_CAP_ID_MSIX, > + .grp_type = GRP_TYPE_EMU, > + .grp_size = 0x0C, > + .size_init = pt_msix_size_init, > + .emu_reg_tbl = pt_emu_reg_msix_tbl, > + }, > { > .grp_size = 0, > }, > @@ -1478,6 +1950,14 @@ void pt_config_delete(XenPCIPassthroughState *s) > struct XenPTRegGroup *reg_group, *next_grp; > struct XenPTReg *reg, *next_reg; > > + /* free MSI/MSI-X info table */ > + if (s->msix) { > + pt_msix_delete(s); > + } > + if (s->msi) { > + g_free(s->msi); > + } > + > /* free all register group entry */ > QLIST_FOREACH_SAFE(reg_group, &s->reg_grp_tbl, entries, next_grp) { > /* free all register entry */ > diff --git a/hw/xen_pci_passthrough_msi.c b/hw/xen_pci_passthrough_msi.c > new file mode 100644 > index 0000000..0b81060 > --- /dev/null > +++ b/hw/xen_pci_passthrough_msi.c > @@ -0,0 +1,667 @@ > +/* > + * Copyright (c) 2007, Intel Corporation. > + * > + * This work is licensed under the terms of the GNU GPL, version 2. See > + * the COPYING file in the top-level directory. > + * > + * Jiang Yunhong <yunhong.jiang@xxxxxxxxx> > + * > + * This file implements direct PCI assignment to a HVM guest > + */ > + > +#include <sys/mman.h> > + > +#include "xen_backend.h" > +#include "xen_pci_passthrough.h" > +#include "apic-msidef.h" > + > + > +#define AUTO_ASSIGN -1 > + > +/* shift count for gflags */ > +#define GFLAGS_SHIFT_DEST_ID 0 > +#define GFLAGS_SHIFT_RH 8 > +#define GFLAGS_SHIFT_DM 9 > +#define GLFAGS_SHIFT_DELIV_MODE 12 > +#define GLFAGS_SHIFT_TRG_MODE 15 > + > + > +/* > + * Helpers > + */ > + > +static inline uint8_t msi_vector(uint32_t data) > +{ > + return (data & MSI_DATA_VECTOR_MASK) >> MSI_DATA_VECTOR_SHIFT; > +} > + > +static inline uint8_t msi_dest_id(uint32_t addr) > +{ > + return (addr & MSI_ADDR_DEST_ID_MASK) >> MSI_ADDR_DEST_ID_SHIFT; > +} > + > +static inline uint32_t msi_ext_dest_id(uint32_t addr_hi) > +{ > + return addr_hi & 0xffffff00; > +} > + > +static uint32_t msi_gflags(uint32_t data, uint64_t addr) > +{ > + uint32_t result = 0; > + int rh, dm, dest_id, deliv_mode, trig_mode; > + > + rh = (addr >> MSI_ADDR_REDIRECTION_SHIFT) & 0x1; > + dm = (addr >> MSI_ADDR_DEST_MODE_SHIFT) & 0x1; > + dest_id = msi_dest_id(addr); > + deliv_mode = (data >> MSI_DATA_DELIVERY_MODE_SHIFT) & 0x7; > + trig_mode = (data >> MSI_DATA_TRIGGER_SHIFT) & 0x1; > + > + result = dest_id | (rh << GFLAGS_SHIFT_RH) | (dm << GFLAGS_SHIFT_DM) | > + (deliv_mode << GLFAGS_SHIFT_DELIV_MODE) | > + (trig_mode << GLFAGS_SHIFT_TRG_MODE); > + > + return result; > +} > + > +static inline uint64_t msi_addr64(XenPTMSI *msi) > +{ > + return (uint64_t)msi->addr_hi << 32 | msi->addr_lo; > +} > + > +static int msi_msix_enable(XenPCIPassthroughState *s, > + uint32_t address, > + uint16_t flag, > + bool enable) > +{ > + uint16_t val = 0; > + > + if (!address) { > + return -1; > + } > + > + host_pci_get_word(s->real_device, address, &val); > + if (enable) { > + val |= flag; > + } else { > + val &= ~flag; > + } > + host_pci_set_word(s->real_device, address, val); > + return 0; > +} > + > +static int msi_msix_setup(XenPCIPassthroughState *s, > + uint64_t addr, > + uint32_t data, > + int *ppirq, > + bool is_msix, > + int msix_entry, > + bool is_not_mapped) > +{ > + uint8_t gvec = msi_vector(data); > + int rc = 0; > + > + assert((!is_msix && msix_entry == 0) || is_msix); > + > + if (gvec == 0) { > + /* if gvec is 0, the guest is asking for a particular pirq that > + * is passed as dest_id */ > + *ppirq = msi_ext_dest_id(addr >> 32) | msi_dest_id(addr); > + if (!*ppirq) { > + /* this probably identifies an misconfiguration of the guest, > + * try the emulated path */ > + *ppirq = PT_UNASSIGNED_PIRQ; > + } else { > + PT_LOG(&s->dev, "requested pirq %d for MSI%s" > + " (vec: %#x, entry: %#x)\n", > + *ppirq, is_msix ? "-X" : "", gvec, msix_entry); > + } > + } > + > + if (is_not_mapped) { > + uint64_t table_base = 0; > + > + if (is_msix) { > + table_base = s->msix->table_base; > + } > + > + rc = xc_physdev_map_pirq_msi(xen_xc, xen_domid, AUTO_ASSIGN, ppirq, > + PCI_DEVFN(s->real_device->dev, > + s->real_device->func), > + s->real_device->bus, > + msix_entry, table_base); > + if (rc) { > + PT_ERR(&s->dev, "Mapping of MSI%s (rc: %i, vec: %#x, entry > %#x)\n", > + is_msix ? "-X" : "", rc, gvec, msix_entry); > + return rc; > + } > + } > + > + return 0; > +} > +static int msi_msix_update(XenPCIPassthroughState *s, > + uint64_t addr, > + uint32_t data, > + int pirq, > + bool is_msix, > + int msix_entry, > + int *old_pirq) > +{ > + PCIDevice *d = &s->dev; > + uint8_t gvec = msi_vector(data); > + uint32_t gflags = msi_gflags(data, addr); > + int rc = 0; > + uint64_t table_addr = 0; > + > + PT_LOG(d, "Updating MSI%s with pirq %d gvec %#x gflags %#x (entry: > %#x)\n", > + is_msix ? "-X" : "", pirq, gvec, gflags, msix_entry); > + > + if (is_msix) { > + table_addr = s->msix->mmio_base_addr; > + } > + > + rc = xc_domain_update_msi_irq(xen_xc, xen_domid, gvec, > + pirq, gflags, table_addr); > + > + if (rc) { > + PT_ERR(d, "Updating of MSI%s failed. (rc: %d)\n", > + is_msix ? "-X" : "", rc); > + > + if (xc_physdev_unmap_pirq(xen_xc, xen_domid, *old_pirq)) { > + PT_ERR(d, "Unmapping of MSI%s pirq %d failed.\n", > + is_msix ? "-X" : "", *old_pirq); > + } > + *old_pirq = PT_UNASSIGNED_PIRQ; > + } > + return rc; > +} > + > +static int msi_msix_disable(XenPCIPassthroughState *s, > + uint64_t addr, > + uint32_t data, > + int pirq, > + bool is_msix, > + bool is_binded) > +{ > + PCIDevice *d = &s->dev; > + uint8_t gvec = msi_vector(data); > + uint32_t gflags = msi_gflags(data, addr); > + int rc = 0; > + > + if (pirq == PT_UNASSIGNED_PIRQ) { > + return 0; > + } > + > + if (is_binded) { > + PT_LOG(d, "Unbind MSI%s with pirq %d, gvec %#x\n", > + is_msix ? "-X" : "", pirq, gvec); > + rc = xc_domain_unbind_msi_irq(xen_xc, xen_domid, gvec, pirq, > gflags); > + if (rc) { > + PT_ERR(d, "Unbinding of MSI%s failed. (pirq: %d, gvec: %#x)\n", > + is_msix ? "-X" : "", pirq, gvec); > + return rc; > + } > + } > + > + PT_LOG(d, "Unmap MSI%s pirq %d\n", is_msix ? "-X" : "", pirq); > + rc = xc_physdev_unmap_pirq(xen_xc, xen_domid, pirq); > + if (rc) { > + PT_ERR(d, "Unmapping of MSI%s pirq %d failed. (rc: %i)\n", > + is_msix ? "-X" : "", pirq, rc); > + return rc; > + } > + > + return 0; > +} > + > +/* > + * MSI virtualization functions > + */ > + > +int pt_msi_set_enable(XenPCIPassthroughState *s, bool enable) > +{ > + PT_LOG(&s->dev, "%s MSI.\n", enable ? "enabling" : "disabling"); > + > + if (!s->msi) { > + return -1; > + } > + > + return msi_msix_enable(s, s->msi->ctrl_offset, PCI_MSI_FLAGS_ENABLE, > + enable); > +} > + > +/* setup physical msi, but don't enable it */ > +int pt_msi_setup(XenPCIPassthroughState *s) > +{ > + int pirq = PT_UNASSIGNED_PIRQ; > + int rc = 0; > + XenPTMSI *msi = s->msi; > + > + if (msi->initialized) { > + PT_ERR(&s->dev, > + "Setup physical MSI when it has been properly > initialized.\n"); > + return -1; > + } > + > + rc = msi_msix_setup(s, msi_addr64(msi), msi->data, &pirq, false, 0, > true); > + if (rc) { > + return rc; > + } > + > + if (pirq < 0) { > + PT_ERR(&s->dev, "Invalid pirq number: %d.\n", pirq); > + return -1; > + } > + > + msi->pirq = pirq; > + PT_LOG(&s->dev, "MSI mapped with pirq %d.\n", pirq); > + > + return 0; > +} > + > +int pt_msi_update(XenPCIPassthroughState *s) > +{ > + XenPTMSI *msi = s->msi; > + return msi_msix_update(s, msi_addr64(msi), msi->data, msi->pirq, > + false, 0, &msi->pirq); > +} > + > +void pt_msi_disable(XenPCIPassthroughState *s) > +{ > + XenPTMSI *msi = s->msi; > + > + if (!msi) { > + return; > + } > + > + pt_msi_set_enable(s, false); > + > + msi_msix_disable(s, msi_addr64(msi), msi->data, msi->pirq, false, > + msi->initialized); > + > + /* clear msi info */ > + msi->flags = 0; > + msi->mapped = false; > + msi->pirq = PT_UNASSIGNED_PIRQ; > +} > + > +/* > + * MSI-X virtualization functions > + */ > + > +static int msix_set_enable(XenPCIPassthroughState *s, bool enabled) > +{ > + PT_LOG(&s->dev, "%s MSI-X.\n", enabled ? "enabling" : "disabling"); > + > + if (!s->msix) { > + return -1; > + } > + > + return msi_msix_enable(s, s->msix->ctrl_offset, PCI_MSIX_FLAGS_ENABLE, > + enabled); > +} > + > +static void mask_physical_msix_entry(XenPCIPassthroughState *s, > + int entry_nr, int mask) > +{ > + void *phys_off; > + > + phys_off = s->msix->phys_iomem_base + PCI_MSIX_ENTRY_SIZE * entry_nr > + + PCI_MSIX_ENTRY_VECTOR_CTRL; > + *(uint32_t *)phys_off = mask; > +} > + > +static int pt_msix_update_one(XenPCIPassthroughState *s, int entry_nr) > +{ > + XenPTMSIXEntry *entry = NULL; > + int pirq; > + int rc; > + > + if (entry_nr < 0 || entry_nr >= s->msix->total_entries) { > + return -EINVAL; > + } > + > + entry = &s->msix->msix_entry[entry_nr]; > + > + if (!entry->updated) { > + return 0; > + } > + > + pirq = entry->pirq; > + > + rc = msi_msix_setup(s, entry->data, entry->data, &pirq, true, entry_nr, > + entry->pirq == PT_UNASSIGNED_PIRQ); > + if (rc) { > + return rc; > + } > + if (entry->pirq == PT_UNASSIGNED_PIRQ) { > + entry->pirq = pirq; > + } > + > + rc = msi_msix_update(s, entry->addr, entry->data, pirq, true, > + entry_nr, &entry->pirq); > + > + if (!rc) { > + entry->updated = false; > + } > + > + return rc; > +} > + > +int pt_msix_update(XenPCIPassthroughState *s) > +{ > + XenPTMSIX *msix = s->msix; > + int i; > + > + for (i = 0; i < msix->total_entries; i++) { > + pt_msix_update_one(s, i); > + } > + > + return 0; > +} > + > +void pt_msix_disable(XenPCIPassthroughState *s) > +{ > + int i = 0; > + > + msix_set_enable(s, false); > + > + for (i = 0; i < s->msix->total_entries; i++) { > + XenPTMSIXEntry *entry = &s->msix->msix_entry[i]; > + > + msi_msix_disable(s, entry->addr, entry->data, entry->pirq, true, > true); > + > + /* clear MSI-X info */ > + entry->pirq = PT_UNASSIGNED_PIRQ; > + entry->updated = false; > + } > +} > + > +int pt_msix_update_remap(XenPCIPassthroughState *s, int bar_index) > +{ > + XenPTMSIXEntry *entry; > + int i, ret; > + > + if (!(s->msix && s->msix->bar_index == bar_index)) { > + return 0; > + } > + > + for (i = 0; i < s->msix->total_entries; i++) { > + entry = &s->msix->msix_entry[i]; > + if (entry->pirq != PT_UNASSIGNED_PIRQ) { > + ret = xc_domain_unbind_pt_irq(xen_xc, xen_domid, entry->pirq, > + PT_IRQ_TYPE_MSI, 0, 0, 0, 0); > + if (ret) { > + PT_ERR(&s->dev, "unbind MSI-X entry %d failed\n", > entry->pirq); > + } > + entry->updated = true; > + } > + } > + pt_msix_update(s); > + > + return 0; > +} > + > +static uint32_t get_entry_value(XenPTMSIXEntry *e, int offset) > +{ > + switch (offset) { > + case PCI_MSIX_ENTRY_LOWER_ADDR: > + return e->addr & UINT32_MAX; > + case PCI_MSIX_ENTRY_UPPER_ADDR: > + return e->addr >> 32; > + case PCI_MSIX_ENTRY_DATA: > + return e->data; > + case PCI_MSIX_ENTRY_VECTOR_CTRL: > + return e->vector_ctrl; > + default: > + return 0; > + } > +} > + > +static void set_entry_value(XenPTMSIXEntry *e, int offset, uint32_t val) > +{ > + switch (offset) { > + case PCI_MSIX_ENTRY_LOWER_ADDR: > + e->addr = (e->addr & ((uint64_t)UINT32_MAX << 32)) | val; > + break; > + case PCI_MSIX_ENTRY_UPPER_ADDR: > + e->addr = (uint64_t)val << 32 | (e->addr & UINT32_MAX); > + break; > + case PCI_MSIX_ENTRY_DATA: > + e->data = val; > + break; > + case PCI_MSIX_ENTRY_VECTOR_CTRL: > + e->vector_ctrl = val; > + break; > + } > +} > + > +static void pci_msix_write(void *opaque, target_phys_addr_t addr, > + uint64_t val, unsigned size) > +{ > + XenPCIPassthroughState *s = opaque; > + XenPTMSIX *msix = s->msix; > + XenPTMSIXEntry *entry; > + int entry_nr, offset; > + > + entry_nr = addr / PCI_MSIX_ENTRY_SIZE; > + if (entry_nr < 0 || entry_nr >= msix->total_entries) { > + PT_ERR(&s->dev, "asked MSI-X entry '%i' invalid!\n", entry_nr); > + return; > + } > + entry = &msix->msix_entry[entry_nr]; > + offset = addr % PCI_MSIX_ENTRY_SIZE; > + > + if (offset != PCI_MSIX_ENTRY_VECTOR_CTRL) { > + const volatile uint32_t *vec_ctrl; > + > + if (get_entry_value(entry, offset) == val) { > + return; > + } > + > + /* > + * If Xen intercepts the mask bit access, entry->vec_ctrl may not be > + * up-to-date. Read from hardware directly. > + */ > + vec_ctrl = s->msix->phys_iomem_base + entry_nr * PCI_MSIX_ENTRY_SIZE > + + PCI_MSIX_ENTRY_VECTOR_CTRL; > + > + if (msix->enabled && !(*vec_ctrl & PCI_MSIX_ENTRY_CTRL_MASKBIT)) { > + PT_ERR(&s->dev, "Can't update msix entry %d since MSI-X is > already > " > + "enabled.\n", entry_nr); > + return; > + } > + > + entry->updated = true; > + } > + > + set_entry_value(entry, offset, val); > + > + if (offset == PCI_MSIX_ENTRY_VECTOR_CTRL) { > + if (msix->enabled && !(val & PCI_MSIX_ENTRY_CTRL_MASKBIT)) { > + pt_msix_update_one(s, entry_nr); > + } > + mask_physical_msix_entry(s, entry_nr, > + entry->vector_ctrl & PCI_MSIX_ENTRY_CTRL_MASKBIT); > + } > +} > + > +static uint64_t pci_msix_read(void *opaque, target_phys_addr_t addr, > + unsigned size) > +{ > + XenPCIPassthroughState *s = opaque; > + XenPTMSIX *msix = s->msix; > + int entry_nr, offset; > + > + entry_nr = addr / PCI_MSIX_ENTRY_SIZE; > + if (entry_nr < 0 || entry_nr >= msix->total_entries) { > + PT_ERR(&s->dev, "asked MSI-X entry '%i' invalid!\n", entry_nr); > + return 0; > + } > + > + offset = addr % PCI_MSIX_ENTRY_SIZE; > + > + return get_entry_value(&msix->msix_entry[entry_nr], offset); > +} > + > +static const MemoryRegionOps pci_msix_ops = { > + .read = pci_msix_read, > + .write = pci_msix_write, > + .endianness = DEVICE_NATIVE_ENDIAN, > + .valid = { > + .min_access_size = 4, > + .max_access_size = 4, > + .unaligned = false, > + }, > +}; > + > +int pt_add_msix_mapping(XenPCIPassthroughState *s, int bar_index) > +{ > + XenPTMSIX *msix = s->msix; > + > + if (!(s->msix && s->msix->bar_index == bar_index)) { > + return 0; > + } > + > + memory_region_set_enabled(&msix->mmio, false); > + return xc_domain_memory_mapping(xen_xc, xen_domid, > + s->msix->mmio_base_addr >> XC_PAGE_SHIFT, > + (s->bases[bar_index].access.maddr + s->msix->table_off) > + >> XC_PAGE_SHIFT, > + (s->msix->total_entries * PCI_MSIX_ENTRY_SIZE + XC_PAGE_SIZE - 1) > + >> XC_PAGE_SHIFT, > + DPCI_ADD_MAPPING); > +} > + > +int pt_remove_msix_mapping(XenPCIPassthroughState *s, int bar_index) > +{ > + XenPTMSIX *msix = s->msix; > + > + if (!(msix && msix->bar_index == bar_index)) { > + return 0; > + } > + > + memory_region_set_enabled(&msix->mmio, true); > + > + msix->mmio_base_addr = s->bases[bar_index].e_physbase + msix->table_off; > + > + return xc_domain_memory_mapping(xen_xc, xen_domid, > + s->msix->mmio_base_addr >> XC_PAGE_SHIFT, > + (s->bases[bar_index].access.maddr + s->msix->table_off) > + >> XC_PAGE_SHIFT, > + (s->msix->total_entries * PCI_MSIX_ENTRY_SIZE + XC_PAGE_SIZE - 1) > + >> XC_PAGE_SHIFT, > + DPCI_REMOVE_MAPPING); > +} > + > +int pt_msix_init(XenPCIPassthroughState *s, uint32_t base) > +{ > + uint8_t id = 0; > + uint16_t control = 0; > + uint32_t table_off = 0; > + int i, total_entries, bar_index; > + HostPCIDevice *hd = s->real_device; > + PCIDevice *d = &s->dev; > + int fd = -1; > + XenPTMSIX *msix = NULL; > + int rc = 0; > + > + rc = host_pci_get_byte(hd, base + PCI_CAP_LIST_ID, &id); > + if (rc) { > + return rc; > + } > + > + if (id != PCI_CAP_ID_MSIX) { > + PT_ERR(d, "Invalid id %#x base %#x\n", id, base); > + return -1; > + } > + > + host_pci_get_word(hd, base + PCI_MSIX_FLAGS, &control); > + total_entries = control & PCI_MSIX_FLAGS_QSIZE; > + total_entries += 1; > + > + s->msix = g_malloc0(sizeof (XenPTMSIX) > + + total_entries * sizeof (XenPTMSIXEntry)); > + msix = s->msix; > + > + msix->total_entries = total_entries; > + for (i = 0; i < total_entries; i++) { > + msix->msix_entry[i].pirq = PT_UNASSIGNED_PIRQ; > + } > + > + memory_region_init_io(&msix->mmio, &pci_msix_ops, s, "passthrough-msix", > + total_entries * PCI_MSIX_ENTRY_SIZE); > + > + host_pci_get_long(hd, base + PCI_MSIX_TABLE, &table_off); > + bar_index = msix->bar_index = table_off & PCI_MSIX_FLAGS_BIRMASK; > + table_off = msix->table_off = table_off & ~PCI_MSIX_FLAGS_BIRMASK; > + msix->table_base = s->real_device->io_regions[bar_index].base_addr; > + PT_LOG(d, "get MSI-X table BAR base 0x%"PRIx64"\n", msix->table_base); > + > + fd = open("/dev/mem", O_RDWR); > + if (fd == -1) { > + rc = -errno; > + PT_ERR(d, "Can't open /dev/mem: %s\n", strerror(errno)); > + goto error_out; > + } > + PT_LOG(d, "table_off = %#x, total_entries = %d\n", > + table_off, total_entries); > + msix->table_offset_adjust = table_off & 0x0fff; > + msix->phys_iomem_base = > + mmap(NULL, > + total_entries * PCI_MSIX_ENTRY_SIZE + msix->table_offset_adjust, > + PROT_WRITE | PROT_READ, > + MAP_SHARED | MAP_LOCKED, > + fd, > + msix->table_base + table_off - msix->table_offset_adjust); > + > + if (msix->phys_iomem_base == MAP_FAILED) { > + rc = -errno; > + PT_ERR(d, "Can't map physical MSI-X table: %s\n", strerror(errno)); > + close(fd); > + goto error_out; > + } > + msix->phys_iomem_base = (char *)msix->phys_iomem_base > + + msix->table_offset_adjust; > + > + close(fd); > + > + PT_LOG(d, "mapping physical MSI-X table to %p\n", msix->phys_iomem_base); > + > + memory_region_transaction_begin(); > + memory_region_add_subregion_overlap(&s->bar[bar_index], msix->table_off, > + &msix->mmio, > + 2); /* Priority: pci default + 1 */ > + memory_region_set_enabled(&msix->mmio, false); > + memory_region_transaction_commit(); > + > + return 0; > + > +error_out: > + memory_region_destroy(&msix->mmio); > + g_free(s->msix); > + s->msix = NULL; > + return rc; > +} > + > +void pt_msix_delete(XenPCIPassthroughState *s) > +{ > + XenPTMSIX *msix = s->msix; > + > + if (!msix) { > + return; > + } > + > + /* unmap the MSI-X memory mapped register area */ > + if (msix->phys_iomem_base) { > + PT_LOG(&s->dev, "unmapping physical MSI-X table from %p\n", > + msix->phys_iomem_base); > + munmap(msix->phys_iomem_base, msix->total_entries * > PCI_MSIX_ENTRY_SIZE > + + msix->table_offset_adjust); > + } > + > + memory_region_del_subregion(&s->bar[msix->bar_index], &msix->mmio); > + memory_region_destroy(&msix->mmio); > + > + g_free(s->msix); > + s->msix = NULL; > +} > -- > Anthony PERARD > > > _______________________________________________ > Xen-devel mailing list > Xen-devel@xxxxxxxxxxxxxxxxxxx > http://lists.xensource.com/xen-devel _______________________________________________ Xen-devel mailing list Xen-devel@xxxxxxxxxxxxxxxxxxx http://lists.xensource.com/xen-devel
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