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[Date Prev][Date Next][Thread Prev][Thread Next][Date Index][Thread Index] [Xen-devel] [PATCH 11/14] arm: add files that are required to support the Tegra2 harmony board.
arm: add files that are required to support the Tegra2 harmony board.
xen/arch/arm/tegra/Makefile | 3 +-
xen/arch/arm/tegra/entry.S | 33 ++++++++
xen/arch/arm/tegra/tegra250.c | 330
+++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
xen/arch/arm/tegra/timer.c | 110 +++++++++++++++++++++++++++
xen/arch/arm/xen/cpu.c | 5 +
xen/arch/arm/xen/fault.c | 1 -
xen/arch/arm/xen/irq.c | 46 +++++++++++-
xen/arch/arm/xen/mm.c | 24 ++++++
xen/arch/arm/xen/setup.c | 6 +-
xen/arch/arm/xen/time.c | 1 -
xen/drivers/char/console.c | 4 +
xen/include/asm-arm/gic.h | 101 +++++++++++++++++++++++++
xen/include/asm-arm/irq.h | 3 +-
xen/include/asm-arm/tegra/avp.h | 144 ++++++++++++++++++++++++++++++++++++
xen/include/asm-arm/tegra/config.h | 7 +-
xen/include/asm-arm/tegra/irqs.h | 60 +++++++++++++++
xen/include/asm-arm/tegra/smp.h | 7 +
xen/include/asm-arm/tegra/tegra.h | 75 ++++++++++++++++++
xen/include/xen/irq.h | 6 +
19 files changed, 952 insertions(+), 14 deletions(-)
Signed-off-by: Jaemin Ryu <jm77.ryu@xxxxxxxxxxx>
diff -r 6af8a89c99cd xen/arch/arm/tegra/Makefile
--- a/xen/arch/arm/tegra/Makefile Sun Feb 12 12:24:21 2012 +0900
+++ b/xen/arch/arm/tegra/Makefile Sun Feb 12 15:04:06 2012 +0900
@@ -1,1 +1,2 @@
-obj-y += dummy.o
+obj-y += timer.o entry.o tegra250.o
+
diff -r 6af8a89c99cd xen/arch/arm/tegra/entry.S
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/xen/arch/arm/tegra/entry.S Sun Feb 12 15:04:06 2012 +0900
@@ -0,0 +1,33 @@
+/*
+ * entry.S
+ *
+ * Copyright (C) 2008 Samsung Electronics
+ * JaeMin Ryu <jm77.ryu@xxxxxxxxxxx>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public version 2 of License as
published by
+ * the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
+ */
+
+#include <xen/config.h>
+#inlcude <asm/arch/irqs.h>
+#include <asm/page.h>
+#include <asm/system.h>
+#include <asm/asm-macros.h>
+#include <asm/cpu-domain.h>
+#include <asm/asm-offsets.h>
+
+ .align 5
+
+ENTRY(arch_context_switch)
+ mov pc, lr
+
diff -r 6af8a89c99cd xen/arch/arm/tegra/tegra250.c
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/xen/arch/arm/tegra/tegra250.c Sun Feb 12 15:04:06 2012 +0900
@@ -0,0 +1,330 @@
+/*
+ * tegra250.c
+ *
+ * Copyright (C) 2008-2011 Samsung Electronics
+ * JaeMin Ryu <jm77.ryu@xxxxxxxxxxx>
+ *
+ * Secure Xen on ARM architecture designed by Sang-bum Suh consists of
+ * Xen on ARM and the associated access control.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public version 2 of License as
published by
+ * the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
+ */
+
+#include <xen/config.h>
+#include <xen/spinlock.h>
+#include <xen/lib.h>
+#include <xen/serial.h>
+#include <xen/errno.h>
+#include <xen/smp.h>
+#include <xen/irq.h>
+#include <xen/mm.h>
+#include <asm/mmu.h>
+#include <asm/platform.h>
+#include <asm/gic.h>
+#include <asm/regs.h>
+#include <asm/io.h>
+#include <asm/flushtlb.h>
+#include <asm/arch/tegra.h>
+#include <asm/arch/irqs.h>
+
+#define TEGRA250_MEMORY_BASE 0x00000000UL
+#define TEGRA250_MEMORY_SIZE 0x40000000UL
+
+#define TEGRA250_DEV_BASE 0x50000000UL
+#define TEGRA250_DEV_SIZE 0x00300000UL
+
+DECLARE_MEMORY_MAP(tegra250) = {
+ MEMMAP_ENTRY(TEGRA250_MEMORY_BASE, TEGRA250_MEMORY_SIZE,
MEMORY_TYPE_RAM, L1E_TYPE_HYPERVISOR),
+ MEMMAP_ENTRY(TEGRA250_DEV_BASE, TEGRA250_DEV_SIZE,
MEMORY_TYPE_DEV, L1E_TYPE_DEVICE)
+};
+
+// Register APBDMA_IRQ_MASK_CLR_0
+#define APBDMA_IRQ_STA_CPU_0 (0x14)
+#define APBDMA_IRQ_MASK_SET_0 (0x20)
+#define APBDMA_IRQ_MASK_CLR_0 (0x24)
+
+void *tegra_gic_cpu_base[MAX_PHYS_CPUS] = {0, 0};
+void *tegra_gic_dist_base = 0;
+
+struct tegra_irq_ctrl {
+ unsigned int irq_start;
+ void *reg;
+};
+
+static struct tegra_irq_ctrl tegra_irq_ctrl[(INT_SYS_NR + INT_SYS_SZ - 1) /
INT_SYS_SZ];
+
+#define gic_irq(irq) (irq)
+
+static void tegra_mask(struct irq_desc *desc)
+{
+ struct tegra_irq_ctrl *chip;
+ unsigned int irq = desc_to_irq(desc);
+ unsigned int mask = 1 << (irq % 32);
+
+ mmio_writel(mask, tegra_gic_dist_base + _ICDICER + (gic_irq(irq) / 32)
* 4);
+
+ irq -= INT_PRI_BASE;
+ chip = &tegra_irq_ctrl[irq / INT_SYS_SZ];
+ mmio_writel(1 << (irq & 31), chip->reg + ICTLR_CPU_IER_CLR_0);
+}
+
+static void tegra_unmask(struct irq_desc *desc)
+{
+ struct tegra_irq_ctrl *chip;
+ unsigned int irq = desc_to_irq(desc);
+ unsigned int mask = 1 << (irq % 32);
+
+ mmio_writel(mask, tegra_gic_dist_base + _ICDISER + (gic_irq(irq) / 32)
* 4);
+
+ irq -= INT_PRI_BASE;
+ chip = &tegra_irq_ctrl[irq / INT_SYS_SZ];
+ mmio_writel(1 << (irq & 31), chip->reg + ICTLR_CPU_IER_SET_0);
+}
+
+static void tegra_ack(struct irq_desc *desc)
+{
+ unsigned int irq = desc_to_irq(desc);
+ unsigned int mask = 1 << (irq % 32);
+ unsigned int cpu = smp_processor_id();
+
+ tegra_mask(desc);
+
+ mmio_writel(mask, tegra_gic_dist_base + _ICDICER + (gic_irq(irq) / 32)
* 4);
+ mmio_writel(gic_irq(irq), tegra_gic_cpu_base[cpu] + _ICCEOIR);
+}
+
+static void tegra_end(struct irq_desc *desc)
+{
+ tegra_unmask(desc);
+}
+
+hw_irq_controller tegra_irq_controller = {
+ .typename = "level",
+ .startup = tegra_unmask,
+ .shutdown = tegra_mask,
+ .enable = tegra_unmask,
+ .disable = tegra_mask,
+ .ack = tegra_ack,
+ .end = tegra_end,
+};
+
+static void tegra250_irq_init()
+{
+ unsigned int max_irq, i;
+ unsigned int cpu = smp_processor_id();
+ unsigned long cpumask = 1 << cpu;
+
+ for (i = 0; i < ARRAY_SIZE(tegra_irq_ctrl); i++) {
+ tegra_irq_ctrl[i].irq_start = INT_PRI_BASE + INT_SYS_SZ * i;
+ tegra_irq_ctrl[i].reg = IO_ADDRESS(INT_PPI_ADDRESS(i));
+ mmio_writel(0xFFFFFFFF, tegra_irq_ctrl[i].reg +
ICTLR_CPU_IER_CLR_0);
+ mmio_writel(0x00000000, tegra_irq_ctrl[i].reg +
ICTLR_CPU_IEP_CLASS_0);
+ }
+
+ for (i = INT_PRI_BASE; i < INT_GPIO_BASE; i++) {
+ irq_desc[i].handler = &tegra_irq_controller;
+ }
+
+ cpumask |= cpumask << 8;
+ cpumask |= cpumask << 16;
+
+ tegra_gic_dist_base = IO_ADDRESS(TEGRA_ARM_INT_DIST_BASE);
+ tegra_gic_cpu_base[cpu] = IO_ADDRESS(TEGRA_GIC_PROC_IF_BASE);
+
+ mmio_writel(0, tegra_gic_dist_base + _ICDDCR);
+
+ /*
+ * Find out how many interrupts are supported.
+ */
+ max_irq = mmio_readl(tegra_gic_dist_base + _ICDICTR) & 0x1f;
+ max_irq = (max_irq + 1) * 32;
+
+ /*
+ * The GIC only supports up to 1020 interrupt sources.
+ * Limit this to either the architected maximum, or the
+ * platform maximum.
+ */
+ if (max_irq > max(1020, NR_IRQS))
+ max_irq = max(1020, NR_IRQS);
+
+ /*
+ * Set all global interrupts to be level triggered, active low.
+ */
+ for (i = 32; i < max_irq; i += 16)
+ mmio_writel(0, tegra_gic_dist_base + _ICDICFR + i * 4 / 16);
+
+ /*
+ * Set all global interrupts to this CPU only.
+ */
+ for (i = 32; i < max_irq; i += 4)
+ mmio_writel(cpumask, tegra_gic_dist_base + _ICDIPTR + i * 4 /
4);
+ /*
+ * Set priority on all interrupts.
+ */
+ for (i = 0; i < max_irq; i += 4)
+ mmio_writel(0xa0a0a0a0, tegra_gic_dist_base + _ICDIPR + i * 4
/ 4);
+
+ /*
+ * Disable all interrupts.
+ */
+ for (i = 0; i < max_irq; i += 32)
+ mmio_writel(0xffffffff, tegra_gic_dist_base + _ICDICER + i * 4
/ 32);
+
+ mmio_writel(1, tegra_gic_dist_base + _ICDDCR);
+
+ mmio_writel(0xf0, tegra_gic_cpu_base[cpu] + _ICCPMR);
+ mmio_writel(1, tegra_gic_cpu_base[cpu] + _ICCICR);
+
+
+}
+
+#define CLK_RST_CONTROLLER_RST_CPU_CMPLX_CLR_0 (0x344)
+#define CLK_RST_CONTROLLER_CLK_CPU_CMPLX_0 (0x4c)
+#define CPU_CLK_STOP(cpu) (0x1<<(8+cpu))
+#define CPU_RESET(cpu) (0x1011ul<<(cpu))
+
+#define EVP_CPU_RESET_VECTOR_0 (0x100)
+#define FLOW_CTRL_HALT_CPUx_EVENTS(cpu) ((cpu) ? ((cpu - 1) * 0x8 +
0x14) : 0x0)
+
+
+volatile int tegra250_core_map = 1;
+
+asm(
+".type tegra250_slave_cpu_start, #function \n"
+".global tegra250_slave_cpu_start \n"
+"tegra250_slave_cpu_start: \n"
+" msr cpsr_c, #0xD3 \n"
+" mov r0, #0 \n"
+" mcr p15, 2, r0, c0, c0, 0 \n"
+" mrc p15, 1, r0, c0, c0, 0 \n"
+" ldr r1, =0x7FFF \n"
+" and r2, r1, r0, lsr #13 \n"
+" ldr r1, =0x3FF \n"
+" and r3, r1, r0, lsr #3 \n"
+" add r2, r2, #1 \n"
+" and r0, r0, #0x07 \n"
+" add r0, r0, #4 \n"
+" clz r1, r3 \n"
+" add r4, r3, #1 \n"
+"1: sub r2, r2, #1 \n"
+" mov r3, r4 \n"
+"2: subs r3, r3, #1 \n"
+" mov r5, r3, lsl r1 \n"
+" mov r6, r2, lsl r0 \n"
+" orr r5, r5, r6 \n"
+" mcr p15, 0, r5, c7, c6, 2 \n"
+" bgt 2b \n"
+" cmp r2, #0 \n"
+" bgt 1b \n"
+" dsb \n"
+" isb \n"
+" mrc p15, 0, r0, c0, c0, 5 \n"
+" and r0, r0, #15 \n"
+" adr r4, 1f \n"
+" ldmia r4, {r5, r6} \n"
+" sub r4, r4, r5 \n"
+" add r6, r6, r4 \n"
+" mov r1, #1 \n"
+" lsl r1, r1, r0 \n"
+"spin: ldr r7, [r6] \n"
+" tst r7, r1 \n"
+" beq spin \n"
+" b slave_cpu_start \n"
+"1: .long . \n"
+" .long tegra250_core_map \n"
+);
+
+int wakeup_cpu(unsigned int cpu)
+{
+ tegra250_core_map |= 1 << cpu;
+
+ cpu_flush_cache_all();
+
+ return 0;
+}
+
+extern void tegra250_slave_cpu_start(void);
+
+static void tegra250_evp_init(void)
+{
+ unsigned long r, org, loop, ctrl;
+
+ /* Initialize Snoop Control Unit */
+ ctrl = mmio_readl(IO_ADDRESS(TEGRA_SCU_BASE) + 0x0);
+ ctrl |= 1;
+ mmio_writel(ctrl, IO_ADDRESS(TEGRA_SCU_BASE) + 0x0);
+
+ org = mmio_readl(IO_ADDRESS(TEGRA_EXCEPTION_VECTORS_BASE) +
EVP_CPU_RESET_VECTOR_0);
+
+ /* Set boot entry */
+ mmio_writel(__pa(tegra250_slave_cpu_start),
IO_ADDRESS(TEGRA_EXCEPTION_VECTORS_BASE) + EVP_CPU_RESET_VECTOR_0);
+
+ dsb();
+ isb();
+
+ /* Halt CPU */
+ mmio_writel(0, IO_ADDRESS(TEGRA_FLOW_CTRL_BASE) +
FLOW_CTRL_HALT_CPUx_EVENTS(1));
+
+ dsb();
+ isb();
+
+ /* CPU Clock Stop */
+ r = mmio_readl(IO_ADDRESS(TEGRA_CLK_RESET_BASE) +
CLK_RST_CONTROLLER_CLK_CPU_CMPLX_0);
+ r &= ~CPU_CLK_STOP(1);
+ mmio_writel(r, IO_ADDRESS(TEGRA_CLK_RESET_BASE) +
CLK_RST_CONTROLLER_CLK_CPU_CMPLX_0);
+
+ dsb();
+ isb();
+
+ /* Restart Slave CPU */
+ mmio_writel(CPU_RESET(1), IO_ADDRESS(TEGRA_CLK_RESET_BASE) +
CLK_RST_CONTROLLER_RST_CPU_CMPLX_CLR_0);
+
+ dsb();
+ isb();
+
+ /* Wait util the power unit is in stable */
+ loop = 10000;
+ while((--loop) > 0 );
+}
+
+void tegra250_ioremap(void)
+{
+ map_pages_to_xen(IO_ADDRESS(TEGRA_ARM_CPU_BASE),
+ TEGRA_ARM_CPU_BASE >> PAGE_SHIFT, 0x100000 >> PAGE_SHIFT,
+ L1E_TYPE_DEVICE);
+
+ map_pages_to_xen(IO_ADDRESS(TEGRA_PPSB_DEVICE_BASE),
+ TEGRA_PPSB_DEVICE_BASE >> PAGE_SHIFT, 0x100000 >> PAGE_SHIFT,
+ L1E_TYPE_DEVICE);
+
+ map_pages_to_xen(IO_ADDRESS(TEGRA_APB_DEVICE_BASE),
+ TEGRA_APB_DEVICE_BASE >> PAGE_SHIFT, 0x100000 >> PAGE_SHIFT,
+ L1E_TYPE_DEVICE);
+}
+
+int machine_setup(void)
+{
+ cpu_topology_init(2);
+
+ tegra250_ioremap();
+
+ tegra250_evp_init();
+
+ tegra250_irq_init();
+
+ tegra250_timer_init();
+
+ return 0;
+}
+
diff -r 6af8a89c99cd xen/arch/arm/tegra/timer.c
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/xen/arch/arm/tegra/timer.c Sun Feb 12 15:04:06 2012 +0900
@@ -0,0 +1,110 @@
+/*
+ * arch/arm/mach-tegra/timer.c
+ *
+ * Timer and clock event support for NVIDIA Tegra SoCs
+ *
+ * Copyright (c) 2008-2009, NVIDIA Corporation.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
+ * more details.
+ *
+ * You should have received a copy of the GNU General Public License along
+ * with this program; if not, write to the Free Software Foundation, Inc.,
+ * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA.
+ */
+
+#include <xen/sched.h>
+#include <xen/irq.h>
+#include <xen/init.h>
+#include <xen/softirq.h>
+#include <xen/spinlock.h>
+#include <asm/time.h>
+#include <asm/arch/irqs.h>
+#include <asm/arch/tegra.h>
+
+
+#define CLK_RST_CONTROLLER_OSC_CTRL_0 0x50
+
+#define TIMER1_OFFS 0x00 /* reserved for AVP */
+#define TIMER2_OFFS 0x08 /* reserved for AVP */
+#define TIMER3_OFFS 0x50 /* used as OS CPU event timer */
+#define TIMER4_OFFS 0x58 /* reserved as LP2 wakeup trigger
*/
+
+#define TIMER_TMR_PTV_0 0x0
+#define TIMER_TMR_PCR_0 0x4
+
+#define TIMERUS_OFFS 0x10
+#define TIMERUS_CNTR_1US_0 0x0
+#define TIMERUS_USEC_CFG_0 0x4
+
+#define NSEC_PER_SEC 1000000000L
+
+void tegra_clockevent_interrupt(int irq, void *dev_id, struct cpu_user_regs
*regs)
+{
+ mmio_writel(1 << 30, IO_ADDRESS(TEGRA_TMR1_BASE + TIMER3_OFFS) +
TIMER_TMR_PCR_0);
+}
+
+static struct irqaction tegra_clockevent_irq = {
+ .name = "Timer_event",
+ .handler = tegra_clockevent_interrupt,
+};
+
+void tegra_lp2wake_interrupt(int irq, void *dev_id, struct cpu_user_regs *regs)
+{
+ mmio_writel(1<<30, IO_ADDRESS(TEGRA_TMR1_BASE + TIMER4_OFFS) +
TIMER_TMR_PCR_0);
+}
+
+static struct irqaction tegra_lp2wake_irq = {
+ .name = "timer_lp2wake",
+ .handler = tegra_lp2wake_interrupt,
+};
+
+static unsigned long measure_input_freq(unsigned int *m, unsigned int *n)
+{
+ void *clk_rst = IO_ADDRESS(TEGRA_CLK_RESET_BASE);
+ unsigned long osc = mmio_readl(clk_rst + CLK_RST_CONTROLLER_OSC_CTRL_0);
+ osc >>= 30;
+
+ switch (osc) {
+ case 0: if (m && n) { *m=1; *n=13; } return 13000;
+ case 1: if (m && n) { *m=5; *n=96; } return 19200;
+ case 2: if (m && n) { *m=1; *n=12; } return 12000;
+ case 3: if (m && n) { *m=1; *n=26; } return 26000;
+ }
+
+ return 0;
+}
+
+void tegra250_timer_init(void)
+{
+ void *tmr;
+ unsigned int m, n;
+ unsigned long val;
+ u32 reg;
+
+ tmr = IO_ADDRESS(TEGRA_TMR1_BASE + TIMERUS_OFFS);
+ val = measure_input_freq(&m, &n);
+
+ val = ((m-1)<<8) | (n-1);
+
+ mmio_writel(val, tmr + TIMERUS_USEC_CFG_0);
+ mmio_writel(0, IO_ADDRESS(TEGRA_TMR1_BASE + TIMER3_OFFS) +
TIMER_TMR_PTV_0);
+
+ reg = 0xc000270f;
+ mmio_writel(reg, IO_ADDRESS(TEGRA_TMR1_BASE + TIMER3_OFFS) +
TIMER_TMR_PTV_0);
+
+ if (setup_irq(INT_TMR3, &tegra_clockevent_irq)) {
+ BUG();
+ }
+ if (setup_irq(INT_TMR4, &tegra_lp2wake_irq)) {
+ BUG();
+ }
+}
+
diff -r 6af8a89c99cd xen/arch/arm/xen/cpu.c
--- a/xen/arch/arm/xen/cpu.c Sun Feb 12 12:24:21 2012 +0900
+++ b/xen/arch/arm/xen/cpu.c Sun Feb 12 15:04:06 2012 +0900
@@ -53,6 +53,11 @@ int __cpu_up(unsigned int cpu)
{
int ret = 0;
+ ret = wakeup_cpu(cpu);
+ if (!ret) {
+ return -EINVAL;
+ }
+
while(!cpu_online(cpu)) {
cpu_relax();
process_pending_softirqs();
diff -r 6af8a89c99cd xen/arch/arm/xen/fault.c
--- a/xen/arch/arm/xen/fault.c Sun Feb 12 12:24:21 2012 +0900
+++ b/xen/arch/arm/xen/fault.c Sun Feb 12 15:04:06 2012 +0900
@@ -33,7 +33,6 @@
#include <asm/processor.h>
#include <asm/guest_access.h>
#include <asm/system.h>
-#include <asm/memory.h>
asmlinkage void __div0(void)
{
diff -r 6af8a89c99cd xen/arch/arm/xen/irq.c
--- a/xen/arch/arm/xen/irq.c Sun Feb 12 12:24:21 2012 +0900
+++ b/xen/arch/arm/xen/irq.c Sun Feb 12 15:04:06 2012 +0900
@@ -38,9 +38,27 @@ hw_irq_controller no_irq_type = {
.shutdown = irq_shutdown_none,
.enable = irq_enable_none,
.disable = irq_disable_none,
+ .end = irq_end_none,
+ .ack = irq_ack_none,
};
-struct irq_desc *irq_desc;
+//struct irq_desc *irq_desc;
+
+irq_desc_t irq_desc[NR_IRQS] = {
+ [0 ... NR_IRQS - 1] = {
+ .status = IRQ_DISABLED,
+ .handler = &no_irq_type,
+ .action = NULL,
+ .lock = SPIN_LOCK_UNLOCKED
+ }
+};
+
+struct irq_cfg irq_cfg[NR_IRQS] = {
+ [0 ... NR_IRQS - 1] ={
+ .irq = 0
+ }
+};
+
int pirq_guest_unmask(struct domain *d)
{
@@ -75,6 +93,32 @@ struct pirq *alloc_pirq_struct(struct do
return NULL;
}
+int setup_irq(unsigned int irq, struct irqaction *new)
+{
+ unsigned long flags;
+ struct irq_desc *desc;
+
+ if(irq >= NR_IRQS) {
+ printk("BAD IRQ = %d\n", irq);
+ }
+
+ desc = irq_to_desc(irq);
+
+ spin_lock_irqsave(&desc->lock, flags);
+ desc->action = new;
+ if (desc->handler) {
+ if (desc->handler->startup) {
+ desc->handler->startup(desc);
+ } else if(desc->handler->enable) {
+ desc->handler->enable(desc);
+ }
+ }
+
+ spin_unlock_irqrestore(&desc->lock, flags);
+
+ return 0;
+}
+
int arch_init_one_irq_desc(struct irq_desc *desc)
{
NOT_YET();
diff -r 6af8a89c99cd xen/arch/arm/xen/mm.c
--- a/xen/arch/arm/xen/mm.c Sun Feb 12 12:24:21 2012 +0900
+++ b/xen/arch/arm/xen/mm.c Sun Feb 12 15:04:06 2012 +0900
@@ -255,3 +255,27 @@ int alloc_page_map(unsigned long virt, u
return 0;
}
+int map_pages_to_xen(unsigned long virt, unsigned long mfn, int nr, unsigned
long flags)
+{
+ unsigned long vaddr = round_down(virt, PAGE_SIZE);
+ unsigned long maddr = mfn << PAGE_SHIFT;
+ unsigned int end = virt + (nr << PAGE_SHIFT);
+
+ l1e_t *l1e = l1_linear_offset_xen(vaddr);
+
+ do {
+ unsigned long limit = (vaddr + SECTION_SIZE) & (SECTION_MASK);
+ limit = (limit < end) ? limit : end;
+
+ if (((vaddr | maddr | limit) & ~SECTION_MASK) == 0) {
+ *l1e = MK_L1E(maddr, flags);
+ pte_sync(l1e);
+
+ vaddr += SECTION_SIZE;
+ maddr += SECTION_SIZE;
+ }
+ } while(l1e++, vaddr < end);
+
+ return 0;
+}
+
diff -r 6af8a89c99cd xen/arch/arm/xen/setup.c
--- a/xen/arch/arm/xen/setup.c Sun Feb 12 12:24:21 2012 +0900
+++ b/xen/arch/arm/xen/setup.c Sun Feb 12 15:04:06 2012 +0900
@@ -64,11 +64,11 @@ static unsigned int dom0_size = 256 * 10
integer_param("dom0_size", dom0_size);
//static unsigned long dom0_image_start = 0x40B00000UL;
-static unsigned long dom0_image_start = 0x00B00000UL;
+static unsigned long dom0_image_start = 0xA00000UL;
integer_param("image_start", dom0_image_start);
//static unsigned long dom0_image_size = 0xA00000UL;
-static unsigned long dom0_image_size = 0xA00000UL;
+static unsigned long dom0_image_size = 0x1400000UL;
integer_param("image_length", dom0_image_size);
void arch_get_xen_caps(xen_capabilities_info_t *info)
@@ -211,6 +211,8 @@ asmlinkage void start_xen(void)
tasklet_subsys_init();
+ machine_setup();
+
timer_init();
idle_domain_init();
diff -r 6af8a89c99cd xen/arch/arm/xen/time.c
--- a/xen/arch/arm/xen/time.c Sun Feb 12 12:24:21 2012 +0900
+++ b/xen/arch/arm/xen/time.c Sun Feb 12 15:04:06 2012 +0900
@@ -79,5 +79,4 @@ void domain_set_time_offset(struct domai
void timekeeping_init(void)
{
- NOT_YET();
}
diff -r 6af8a89c99cd xen/drivers/char/console.c
--- a/xen/drivers/char/console.c Sun Feb 12 12:24:21 2012 +0900
+++ b/xen/drivers/char/console.c Sun Feb 12 15:04:06 2012 +0900
@@ -412,7 +412,11 @@ long do_console_io(int cmd, int count, X
* *****************************************************
*/
+#if defined(__arm__)
+static bool_t console_locks_busted = 1;
+#else
static bool_t console_locks_busted;
+#endif
static void __putstr(const char *str)
{
diff -r 6af8a89c99cd xen/include/asm-arm/gic.h
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/xen/include/asm-arm/gic.h Sun Feb 12 15:04:06 2012 +0900
@@ -0,0 +1,101 @@
+/*
+ * gic.h
+ *
+ * Copyright (C) 2011 Samsung Electronics
+ * Jaemin Ryu <jm77.ryu@xxxxxxxxxxx>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public version 2 of License as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
+ */
+
+#ifndef __ARM_GIC_H__
+#define __ARM_GIC_H__
+
+
+/* Distributor Register Map */
+#define _ICDDCR 0x000 /* Distributor Control Register */
+#define _ICDICTR 0x004 /* Interrupt Controller Type Register */
+#define _ICDIIDR 0x008 /* Distributor Implementer Id Register */
+#define _ICDISR0 0x080 /* Interrupt Security Register */
+#define _ICDISR1 0x084 /* Interrupt Security Register */
+#define _ICDISR2 0x088 /* Interrupt Security Register */
+#define _ICDISR3 0x08c /* Interrupt Security Register */
+#define _ICDISR4 0x090 /* Interrupt Security Register */
+#define _ICDISER 0x100 /* Interrupt Set-Enable Register */
+#define _ICDICER 0x180 /* Interrupt Clear-Enable Register */
+#define _ICDISPR 0x200 /* Interrupt Set-Pending Register */
+#define _ICDICPR 0x280 /* Interrupt Clear-Pending Register */
+#define _ICDABR 0x300 /* Active Bit Registers */
+#define _ICDIPR 0x400 /* Interrupt Priority Register */
+#define _ICDIPTR 0x800 /* Interrupt Processor Targets Registers */
+#define _ICDICFR 0xC00 /* Interrupt Configuration Registers */
+#define _ICDSGIR 0xF00 /* Software Generated Interrupt Register */
+
+#define ICDDCR() (_ICDDCR)
+#define ICDICTR() (_ICDICTR)
+#define ICDISR(x) (_ICDISR0 + (x / BITS_PER_LONG) * BYTES_PER_LONG)
+#define ICDISER(x) (_ICDISER + (x / BITS_PER_LONG) * BYTES_PER_LONG)
+#define ICDICER(x) (_ICDICER + (x / BITS_PER_LONG) * BYTES_PER_LONG)
+#define ICDISPR(x) (_ICDISPR + (x / BITS_PER_LONG) * BYTES_PER_LONG)
+#define ICDICPR(x) (_ICDICPR + (x / BITS_PER_LONG) * BYTES_PER_LONG)
+#define ICDABR(x) (_ICDABR + (x / BITS_PER_LONG) * BYTES_PER_LONG)
+#define ICDIPR(x) (_ICDIPR + (x / 4) * BYTES_PER_LONG)
+#define ICDIPTR(x) (_ICDIPTR + (x / 4) * BYTES_PER_LONG)
+#define ICDSGIR() (_ICDSGIR)
+
+/* CPU Interface Register Map */
+#define _ICCICR 0x000 /* CPU Interface Control Register */
+#define _ICCPMR 0x004 /* Interrupt Priority Mask Register */
+#define _ICCBPR 0x008 /* Binrary Point Register */
+#define _ICCIAR 0x00C /* Interrupt Acknowledge Register */
+#define _ICCEOIR 0x010 /* End of Interrupt Register */
+#define _ICCRPR 0x014 /* Running Priority Register */
+#define _ICCHPIR 0x018 /* Highest Pending Interrupt Register */
+#define _ICCABPR 0x01C /* Aliased Binary Point Register */
+#define _ICCIIDR 0x0FC /* CPU Interface Id Register */
+
+#define ICCICR() (_ICCICR)
+#define ICCPMR() (_ICCPMR)
+#define ICCBPR() (_ICCBPR)
+#define ICCIAR() (_ICCIAR)
+#define ICCEOIR() (_ICCEOIR)
+#define ICCRPR() (_ICCRPR)
+#define ICCHPIR() (_ICCHPIR)
+#define ICCIIDR() (_ICCIIDR)
+
+#define SECURE_INTERRUPT 0
+#define NONSECURE_INTERRUPT 1
+
+#define SGI(x) (x)
+#define PPI(x) (x + 16)
+#define SPI(x) (x + 32)
+
+#ifndef __ASSEMBLY__
+
+#include <xen/types.h>
+
+#define GIC_DISTRIBUTOR(x) (_gic_distributor_base + x)
+#define GIC_CPU_INTERFACE(x) (_gic_cpu_base + x)
+
+void gic_set_cpu(unsigned int irq, unsigned int mask);
+void gic_set_irq_priority(unsigned int irq, unsigned int priority);
+void gic_ack_irq(unsigned int irq);
+void gic_mask_irq(unsigned int irq);
+void gic_unmask_irq(unsigned int irq);
+void gic_end_irq(unsigned int irq);
+void gic_change_irq_state(unsigned int irq, unsigned int state);
+
+extern void *_gic_cpu_base[NR_CPUS];
+extern void *_gic_distributor_base;
+#endif
+#endif
diff -r 6af8a89c99cd xen/include/asm-arm/irq.h
--- a/xen/include/asm-arm/irq.h Sun Feb 12 12:24:21 2012 +0900
+++ b/xen/include/asm-arm/irq.h Sun Feb 12 15:04:06 2012 +0900
@@ -15,6 +15,7 @@
#define irq_cfg(irq) (&irq_cfg[irq])
#define irq_to_desc(irq) (&irq_desc[irq])
+#define desc_to_irq(desc) ((desc - &irq_desc[0]) / sizeof(struct
irq_desc));
#define IRQ_MAX_GUESTS 7
typedef struct {
@@ -40,8 +41,6 @@ typedef struct {
DECLARE_BITMAP(_bits,NR_IRQS);
} vmask_t;
-extern struct irq_desc *irq_desc;
-
static inline int irq_desc_initialized(struct irq_desc *desc)
{
return 0;
diff -r 6af8a89c99cd xen/include/asm-arm/tegra/avp.h
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/xen/include/asm-arm/tegra/avp.h Sun Feb 12 15:04:06 2012 +0900
@@ -0,0 +1,144 @@
+/*
+ * Copyright (c) 2010 NVIDIA Corporation.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ *
+ * Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ *
+ * Neither the name of the NVIDIA Corporation nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
+ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ */
+
+#ifndef INCLUDED_AVP_H
+#define INCLUDED_AVP_H
+
+#include "ap15/arictlr.h"
+#include "ap15/artimer.h"
+// FIXME: get the ararmev header
+
+// 3 controllers in contiguous memory starting at INTERRUPT_BASE, each
+// controller's aperture is INTERRUPT_SIZE large
+#define INTERRUPT_BASE 0x60004000
+#define INTERRUPT_SIZE 0x100
+#define INTERRUPT_NUM_CONTROLLERS 3
+
+#define INTERRUPT_PENDING( ctlr ) \
+ (INTERRUPT_BASE + ((ctlr) * INTERRUPT_SIZE) + ICTLR_VIRQ_COP_0)
+
+#define INTERRUPT_SET( ctlr ) \
+ (INTERRUPT_BASE + ((ctlr) * INTERRUPT_SIZE) + ICTLR_COP_IER_SET_0)
+
+#define INTERRUPT_CLR( ctlr ) \
+ (INTERRUPT_BASE + ((ctlr) * INTERRUPT_SIZE) + ICTLR_COP_IER_CLR_0)
+
+#define OSC_CTRL ( 0x60006000 + 0x50 )
+#define OSC_FREQ_DET ( 0x60006000 + 0x58 )
+#define OSC_DET_STATUS ( 0x60006000 + 0x5C )
+
+#define TIMER_USEC ( 0x60005010 )
+#define TIMER_CFG ( 0x60005014 )
+#define TIMER_0_BASE ( 0x60005000 )
+#define TIMER_0 ( TIMER_0_BASE + TIMER_TMR_PTV_0 )
+#define TIMER_0_CLEAR ( TIMER_0_BASE + TIMER_TMR_PCR_0 )
+#define TIMER_1_BASE ( 0x60005008 )
+#define TIMER_1 ( TIMER_1_BASE + TIMER_TMR_PTV_0 )
+#define TIMER_1_CLEAR ( TIMER_1_BASE + TIMER_TMR_PCR_0 )
+
+#define CLOCK_RST_LO (0x60006004)
+#define CLOCK_CTLR_HI (0x60006014)
+#define CLOCK_CTLR_LO (0x60006010)
+
+#define CACHE_CTLR (0x6000C000)
+#define CACHE_CONTROL_0 (0x0)
+
+#define PPI_INTR_ID_TIMER_0 (0)
+#define PPI_INTR_ID_TIMER_1 (1)
+#define PPI_INTR_ID_TIMER_2 (9)
+#define PPI_INTR_ID_TIMER_3 (10)
+
+/* flow controller */
+#define FLOW_CONTROLLER (0x60007004)
+
+/* exception vectors */
+#define VECTOR_BASE ( 0x6000F200 )
+#define VECTOR_RESET ( VECTOR_BASE + 0 )
+#define VECTOR_UNDEF ( VECTOR_BASE + 4 )
+#define VECTOR_SWI ( VECTOR_BASE + 8 )
+#define VECTOR_PREFETCH_ABORT ( VECTOR_BASE + 12 )
+#define VECTOR_DATA_ABORT ( VECTOR_BASE + 16 )
+#define VECTOR_IRQ ( VECTOR_BASE + 24 )
+#define VECTOR_FIQ ( VECTOR_BASE + 28 )
+
+#define MODE_DISABLE_INTR 0xc0
+#define MODE_USR 0x10
+#define MODE_FIQ 0x11
+#define MODE_IRQ 0x12
+#define MODE_SVC 0x13
+#define MODE_ABT 0x17
+#define MODE_UND 0x1B
+#define MODE_SYS 0x1F
+
+#define AP15_CACHE_LINE_SIZE 32
+
+#define AP15_APB_L2_CACHE_BASE 0x7000e800
+#define AP15_APB_CLK_RST_BASE 0x60006000
+#define AP15_APB_MISC_BASE 0x70000000
+
+#define AP10_APB_CLK_RST_BASE 0x60006000
+#define AP10_APB_MISC_BASE 0x70000000
+
+#define MMU_TLB_BASE 0xf000f000
+#define MMU_TLB_CACHE_WINDOW_0 0x40
+#define MMU_TLB_CACHE_OPTIONS_0 0x44
+
+#define AP15_PINMUX_CFG_CTL_0 0x70000024
+#define AP15_AVP_JTAG_ENABLE 0xC0
+
+#define PMC_SCRATCH22_REG_LP0 0x7000e4a8
+
+#define AVP_WDT_RESET 0x2F00BAD0
+
+/* Cached to uncached offset for AVP
+ *
+ * Hardware has uncached remap aperture for AVP as AVP doesn't have MMU
+ * but still has cache (named COP cache).
+ *
+ * This aperture moved between AP15 and AP20.
+ */
+#define AP15_CACHED_TO_UNCACHED_OFFSET 0x90000000
+#define AP20_CACHED_TO_UNCACHED_OFFSET 0x80000000
+
+#define APXX_EXT_MEM_START 0x00000000
+#define APXX_EXT_MEM_END 0x40000000
+
+#define APXX_MMIO_START 0x40000000
+#define APXX_MMIO_END 0xFFF00000
+
+#define TXX_EXT_MEM_START 0x80000000
+#define TXX_EXT_MEM_END 0xc0000000
+
+#define TXX_MMIO_START 0x40000000
+#define TXX_MMIO_END 0x80000000
+
+#endif
diff -r 6af8a89c99cd xen/include/asm-arm/tegra/config.h
--- a/xen/include/asm-arm/tegra/config.h Sun Feb 12 12:24:21 2012 +0900
+++ b/xen/include/asm-arm/tegra/config.h Sun Feb 12 15:04:06 2012 +0900
@@ -1,11 +1,6 @@
#ifndef __TEGRA_CONFIG_H__
#define __TEGRA_CONFIG_H__
-#define HZ 100
-#define CLOCK_TICK_RATE 1000000
+#define MAX_PHYS_CPUS 2
-#define MAX_PHYS_CPUS 2
-
-#define BUILTIN_COMMAND_LINE_SIZE 256
-#define BUILTIN_COMMAND_LINE ""
#endif
diff -r 6af8a89c99cd xen/include/asm-arm/tegra/irqs.h
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/xen/include/asm-arm/tegra/irqs.h Sun Feb 12 15:04:06 2012 +0900
@@ -0,0 +1,60 @@
+/*
+ * arch/arm/mach-tegra/include/mach/irqs.h
+ *
+ * Copyright (c) 2009, NVIDIA Corporation.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
+ * more details.
+ *
+ * You should have received a copy of the GNU General Public License along
+ * with this program; if not, write to the Free Software Foundation, Inc.,
+ * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA.
+ */
+
+#ifndef __TEGRA_IRQS_H
+#define __TEGRA_IRQS_H
+
+#define NR_IRQS 512
+
+#define INT_PRI_BASE 32
+#define INT_RTC (INT_PRI_BASE + 2)
+#define INT_USB (INT_PRI_BASE + 20)
+#define INT_USB2 (INT_PRI_BASE + 21)
+#define INT_APB_DMA (INT_PRI_BASE + 26)
+
+#define INT_SEC_BASE (INT_PRI_BASE + 32)
+#define INT_GPIO1 (INT_SEC_BASE + 0)
+#define INT_GPIO2 (INT_SEC_BASE + 1)
+#define INT_GPIO3 (INT_SEC_BASE + 2)
+#define INT_GPIO4 (INT_SEC_BASE + 3)
+#define INT_TMR3 (INT_SEC_BASE + 9)
+#define INT_TMR4 (INT_SEC_BASE + 10)
+#define INT_SYS_STATS_MON (INT_SEC_BASE + 22)
+#define INT_GPIO5 (INT_SEC_BASE + 23)
+
+#define INT_TRI_BASE (INT_SEC_BASE + 32)
+#define INT_KBC (INT_TRI_BASE + 21)
+#define INT_EXTERNAL_PMU (INT_TRI_BASE + 22)
+#define INT_GPIO6 (INT_TRI_BASE + 23)
+#define INT_GPIO7 (INT_TRI_BASE + 25)
+
+#define INT_QUAD_BASE (INT_TRI_BASE + 32)
+#define INT_USB3 (INT_QUAD_BASE + 1)
+
+#define INT_GPIO_BASE (INT_QUAD_BASE + 32)
+#define INT_GPIO_NR (28*8)
+
+#define INT_APBDMA_BASE (INT_GPIO_BASE + INT_GPIO_NR)
+#define INT_APBDMA_NR (16)
+
+#define INT_SYS_NR (INT_GPIO_BASE - INT_PRI_BASE)
+#define INT_SYS_SZ (INT_SEC_BASE - INT_PRI_BASE)
+
+#endif
diff -r 6af8a89c99cd xen/include/asm-arm/tegra/smp.h
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/xen/include/asm-arm/tegra/smp.h Sun Feb 12 15:04:06 2012 +0900
@@ -0,0 +1,7 @@
+#ifndef ASMARM_ARCH_SMP_H
+#define ASMARM_ARCH_SMP_H
+
+
+#include <asm/gic.h>
+
+#endif
diff -r 6af8a89c99cd xen/include/asm-arm/tegra/tegra.h
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/xen/include/asm-arm/tegra/tegra.h Sun Feb 12 15:04:06 2012 +0900
@@ -0,0 +1,75 @@
+#ifndef __TEGRA250_H__
+#define __TEGRA250_H__
+
+#define TEGRA_ARM_CPU_BASE 0x50000000
+#define TEGRA_PPSB_DEVICE_BASE 0x60000000
+#define TEGRA_APB_DEVICE_BASE 0x70000000
+
+#define TEGRA_ARM_PERIF_BASE 0x50040000
+#define TEGRA_ARM_PERIF_SIZE SZ_8K
+
+#define TEGRA_SCU_BASE 0x50040000
+#define TEGRA_SCU_SIZE SZ_256
+
+#define TEGRA_GIC_PROC_IF_BASE 0x50040100
+#define TEGRA_GIC_PROC_IF_SIZE SZ_256
+
+#define TEGRA_ARM_INT_DIST_BASE 0x50041000
+#define TEGRA_ARM_INT_DIST_SIZE SZ_4K
+
+#define TEGRA_PRIMARY_ICTLR_BASE 0x60004000
+#define TEGRA_PRIMARY_ICTLR_SIZE SZ_64
+
+#define TEGRA_SECONDARY_ICTLR_BASE 0x60004100
+#define TEGRA_SECONDARY_ICTLR_SIZE SZ_64
+
+#define TEGRA_TERTIARY_ICTLR_BASE 0x60004200
+#define TEGRA_TERTIARY_ICTLR_SIZE SZ_64
+
+#define TEGRA_QUATERNARY_ICTLR_BASE 0x60004300
+#define TEGRA_QUATERNARY_ICTLR_SIZE SZ_64
+
+#define TEGRA_TMR1_BASE 0x60005000
+#define TEGRA_TMR1_SIZE SZ_8
+
+#define TEGRA_TMR2_BASE 0x60005008
+#define TEGRA_TMR2_SIZE SZ_8
+
+#define TEGRA_TMRUS_BASE 0x60005010
+#define TEGRA_TMRUS_SIZE SZ_64
+
+#define TEGRA_TMR3_BASE 0x60005050
+#define TEGRA_TMR3_SIZE SZ_8
+
+#define TEGRA_TMR4_BASE 0x60005058
+#define TEGRA_TMR4_SIZE SZ_8
+
+#define TEGRA_CLK_RESET_BASE 0x60006000
+#define TEGRA_CLK_RESET_SIZE SZ_4K
+
+#define TEGRA_FLOW_CTRL_BASE 0x60007000
+#define TEGRA_FLOW_CTRL_SIZE 20
+
+#define TEGRA_GPIO_BASE 0x6000D000
+#define TEGRA_GPIO_SIZE SZ_4K
+
+#define TEGRA_EXCEPTION_VECTORS_BASE 0x6000F000
+#define TEGRA_EXCEPTION_VECTORS_SIZE SZ_4K
+
+#define ICTLR_CPU_IER_0 (0x20)
+#define ICTLR_CPU_IER_SET_0 (0x24)
+#define ICTLR_CPU_IER_CLR_0 (0x28)
+#define ICTLR_CPU_IEP_CLASS_0 (0x2C)
+#define ICTLR_COP_IER_0 (0x30)
+#define ICTLR_COP_IER_SET_0 (0x34)
+#define ICTLR_COP_IER_CLR_0 (0x38)
+#define ICTLR_COP_IEP_CLASS_0 (0x3C)
+
+#define ARM_PERIF_BASE (0x50040000)
+
+//#define IO_ADDRESS(x) (((((x) & 0x70000000) >> 8) +
(((x) & 0x0F000000) >> 4)) |((x) & 0xFFFFF) | 0xFB000000 )
+#define IO_ADDRESS(x) ((((x) & 0xF0000000) >> 8) | ((x) &
0xFFFFF) | (0xFB000000 ))
+#define INT_PPI_ADDRESS(_inst) (0x60004000 + (0x100 * (_inst)))
+#define INT_APBDMA_ADDRESS (0x6000a000)
+
+#endif
diff -r 6af8a89c99cd xen/include/xen/irq.h
--- a/xen/include/xen/irq.h Sun Feb 12 12:24:21 2012 +0900
+++ b/xen/include/xen/irq.h Sun Feb 12 15:04:06 2012 +0900
@@ -95,6 +95,10 @@ int arch_init_one_irq_desc(struct irq_de
#define irq_desc_initialized(desc) ((desc)->handler != NULL)
+#if defined(__arm__)
+extern irq_desc_t irq_desc[NR_IRQS];
+#endif
+
#if defined(__ia64__)
extern irq_desc_t irq_desc[NR_VECTORS];
@@ -121,6 +125,8 @@ extern void irq_actor_none(struct irq_de
#define irq_shutdown_none irq_actor_none
#define irq_disable_none irq_actor_none
#define irq_enable_none irq_actor_none
+#define irq_ack_none irq_actor_none
+#define irq_end_none irq_actor_none
struct domain;
struct vcpu;
Attachment:
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