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[Date Prev][Date Next][Thread Prev][Thread Next][Date Index][Thread Index] [Xen-devel] [PATCH 1 of 4] CONFIG: remove CONFIG_SMP #ifdefs
CONFIG_SMP is always enabled and !CONFIG_SMP is not supported. So
simply the code a little by removing all #ifdefs.
Signed-off-by: Andrew Cooper <andrew.cooper3@xxxxxxxxxx>
diff -r eae25241d571 -r 101b0d7ebb00 xen/arch/x86/apic.c
--- a/xen/arch/x86/apic.c
+++ b/xen/arch/x86/apic.c
@@ -145,9 +145,8 @@ void ack_bad_irq(unsigned int irq)
void __init apic_intr_init(void)
{
-#ifdef CONFIG_SMP
smp_intr_init();
-#endif
+
/* self generated IPI for local APIC timer */
set_intr_gate(LOCAL_TIMER_VECTOR, apic_timer_interrupt);
diff -r eae25241d571 -r 101b0d7ebb00 xen/arch/x86/cpu/amd.c
--- a/xen/arch/x86/cpu/amd.c
+++ b/xen/arch/x86/cpu/amd.c
@@ -370,7 +370,6 @@ static void __devinit init_amd(struct cp
{
u32 l, h;
-#ifdef CONFIG_SMP
unsigned long long value;
/* Disable TLB flush filter by setting HWCR.FFDIS on K8
@@ -384,7 +383,6 @@ static void __devinit init_amd(struct cp
value |= 1 << 6;
wrmsrl(MSR_K7_HWCR, value);
}
-#endif
/*
* FIXME: We should handle the K5 here. Set up the write
diff -r eae25241d571 -r 101b0d7ebb00 xen/arch/x86/cpu/mtrr/cyrix.c
--- a/xen/arch/x86/cpu/mtrr/cyrix.c
+++ b/xen/arch/x86/cpu/mtrr/cyrix.c
@@ -279,9 +279,7 @@ cyrix_arr_init(void)
struct set_mtrr_context ctxt;
unsigned char ccr[7];
int ccrc[7] = { 0, 0, 0, 0, 0, 0, 0 };
-#ifdef CONFIG_SMP
int i;
-#endif
/* flush cache and enable MAPEN */
set_mtrr_prepare_save(&ctxt);
@@ -334,14 +332,13 @@ cyrix_arr_init(void)
ccrc[5] = 1;
setCx86(CX86_CCR5, ccr[5]);
}
-#ifdef CONFIG_SMP
+
for (i = 0; i < 7; i++)
ccr_state[i] = ccr[i];
for (i = 0; i < 8; i++)
cyrix_get_arr(i,
&arr_state[i].base, &arr_state[i].size,
&arr_state[i].type);
-#endif
set_mtrr_done(&ctxt); /* flush cache and disable MAPEN */
diff -r eae25241d571 -r 101b0d7ebb00 xen/arch/x86/cpu/mtrr/main.c
--- a/xen/arch/x86/cpu/mtrr/main.c
+++ b/xen/arch/x86/cpu/mtrr/main.c
@@ -142,8 +142,6 @@ struct set_mtrr_data {
*/
int hold_mtrr_updates_on_aps;
-#ifdef CONFIG_SMP
-
static void ipi_handler(void *info)
/* [SUMMARY] Synchronisation handler. Executed by "other" CPUs.
[RETURNS] Nothing.
@@ -175,8 +173,6 @@ static void ipi_handler(void *info)
local_irq_restore(flags);
}
-#endif
-
static inline int types_compatible(mtrr_type type1, mtrr_type type2) {
return type1 == MTRR_TYPE_UNCACHABLE ||
type2 == MTRR_TYPE_UNCACHABLE ||
diff -r eae25241d571 -r 101b0d7ebb00 xen/arch/x86/io_apic.c
--- a/xen/arch/x86/io_apic.c
+++ b/xen/arch/x86/io_apic.c
@@ -513,7 +513,6 @@ static void clear_IO_APIC (void)
}
}
-#ifdef CONFIG_SMP
static void
set_ioapic_affinity_irq(struct irq_desc *desc, const cpumask_t *mask)
{
@@ -550,7 +549,6 @@ set_ioapic_affinity_irq(struct irq_desc
spin_unlock_irqrestore(&ioapic_lock, flags);
}
-#endif /* CONFIG_SMP */
/*
* Find the IRQ entry number of a certain pin.
@@ -630,7 +628,6 @@ static int pin_2_irq(int idx, int apic,
* we need to reprogram the ioredtbls to cater for the cpus which have come
online
* so mask in all cases should simply be TARGET_CPUS
*/
-#ifdef CONFIG_SMP
void /*__init*/ setup_ioapic_dest(void)
{
int pin, ioapic, irq, irq_entry;
@@ -653,7 +650,6 @@ void /*__init*/ setup_ioapic_dest(void)
}
}
-#endif
/*
* EISA Edge/Level control register, ELCR
diff -r eae25241d571 -r 101b0d7ebb00 xen/arch/x86/oprofile/nmi_int.c
--- a/xen/arch/x86/oprofile/nmi_int.c
+++ b/xen/arch/x86/oprofile/nmi_int.c
@@ -304,11 +304,6 @@ static int __init p4_init(char ** cpu_ty
return 0;
}
-#ifndef CONFIG_SMP
- *cpu_type = "i386/p4", XENOPROF_CPU_TYPE_SIZE);
- model = &op_p4_spec;
- return 1;
-#else
switch (current_cpu_data.x86_num_siblings) {
case 1:
*cpu_type = "i386/p4";
@@ -320,7 +315,7 @@ static int __init p4_init(char ** cpu_ty
model = &op_p4_ht2_spec;
return 1;
}
-#endif
+
printk("Xenoprof ERROR: P4 HyperThreading detected with > 2 threads\n");
return 0;
diff -r eae25241d571 -r 101b0d7ebb00 xen/arch/x86/oprofile/op_model_p4.c
--- a/xen/arch/x86/oprofile/op_model_p4.c
+++ b/xen/arch/x86/oprofile/op_model_p4.c
@@ -40,19 +40,13 @@ static unsigned int num_counters = NUM_C
kernel boot-time. */
static inline void setup_num_counters(void)
{
-#ifdef CONFIG_SMP
if (boot_cpu_data.x86_num_siblings == 2) /* XXX */
num_counters = NUM_COUNTERS_HT2;
-#endif
}
static int inline addr_increment(void)
{
-#ifdef CONFIG_SMP
return boot_cpu_data.x86_num_siblings == 2 ? 2 : 1;
-#else
- return 1;
-#endif
}
@@ -383,11 +377,8 @@ static const struct p4_event_binding p4_
or "odd" part of all the divided resources. */
static unsigned int get_stagger(void)
{
-#ifdef CONFIG_SMP
int cpu = smp_processor_id();
return (cpu != cpumask_first(per_cpu(cpu_sibling_mask, cpu)));
-#endif
- return 0;
}
@@ -709,7 +700,6 @@ static void p4_stop(struct op_msrs const
}
-#ifdef CONFIG_SMP
struct op_x86_model_spec const op_p4_ht2_spec = {
.num_counters = NUM_COUNTERS_HT2,
.num_controls = NUM_CONTROLS_HT2,
@@ -719,7 +709,7 @@ struct op_x86_model_spec const op_p4_ht2
.start = &p4_start,
.stop = &p4_stop
};
-#endif
+
struct op_x86_model_spec const op_p4_spec = {
.num_counters = NUM_COUNTERS_NON_HT,
diff -r eae25241d571 -r 101b0d7ebb00 xen/common/rcupdate.c
--- a/xen/common/rcupdate.c
+++ b/xen/common/rcupdate.c
@@ -83,9 +83,7 @@ struct rcu_data {
long blimit; /* Upper limit on a processed batch */
int cpu;
struct rcu_head barrier;
-#ifdef CONFIG_SMP
long last_rs_qlen; /* qlen during the last resched */
-#endif
};
static DEFINE_PER_CPU(struct rcu_data, rcu_data);
diff -r eae25241d571 -r 101b0d7ebb00 xen/include/asm-x86/config.h
--- a/xen/include/asm-x86/config.h
+++ b/xen/include/asm-x86/config.h
@@ -21,7 +21,6 @@
#define CONFIG_X86 1
#define CONFIG_X86_HT 1
#define CONFIG_PAGING_ASSISTANCE 1
-#define CONFIG_SMP 1
#define CONFIG_X86_LOCAL_APIC 1
#define CONFIG_X86_GOOD_APIC 1
#define CONFIG_X86_IO_APIC 1
diff -r eae25241d571 -r 101b0d7ebb00 xen/include/asm-x86/processor.h
--- a/xen/include/asm-x86/processor.h
+++ b/xen/include/asm-x86/processor.h
@@ -189,13 +189,8 @@ struct cpuinfo_x86 {
extern struct cpuinfo_x86 boot_cpu_data;
-#ifdef CONFIG_SMP
extern struct cpuinfo_x86 cpu_data[];
#define current_cpu_data cpu_data[smp_processor_id()]
-#else
-#define cpu_data (&boot_cpu_data)
-#define current_cpu_data boot_cpu_data
-#endif
extern void set_cpuid_faulting(bool_t enable);
diff -r eae25241d571 -r 101b0d7ebb00 xen/include/asm-x86/smp.h
--- a/xen/include/asm-x86/smp.h
+++ b/xen/include/asm-x86/smp.h
@@ -17,7 +17,6 @@
#endif
#define BAD_APICID -1U
-#ifdef CONFIG_SMP
#ifndef __ASSEMBLY__
/*
@@ -65,11 +64,4 @@ void __stop_this_cpu(void);
#endif /* !__ASSEMBLY__ */
-#else /* CONFIG_SMP */
-
-#define cpu_physical_id(cpu) boot_cpu_physical_apicid
-
-#define NO_PROC_ID 0xFF /* No processor magic marker */
-
#endif
-#endif
diff -r eae25241d571 -r 101b0d7ebb00 xen/include/asm-x86/system.h
--- a/xen/include/asm-x86/system.h
+++ b/xen/include/asm-x86/system.h
@@ -154,15 +154,9 @@ static always_inline unsigned long __cmp
#define rmb() barrier()
#define wmb() barrier()
-#ifdef CONFIG_SMP
#define smp_mb() mb()
#define smp_rmb() rmb()
#define smp_wmb() wmb()
-#else
-#define smp_mb() barrier()
-#define smp_rmb() barrier()
-#define smp_wmb() barrier()
-#endif
#define set_mb(var, value) do { xchg(&var, value); } while (0)
#define set_wmb(var, value) do { var = value; wmb(); } while (0)
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