x86/xsave: provide guests with finit-like environment

Without the use of xsave, guests get their initial floating point
environment set up with finit. At least NetWare actually depends on
this (in particular on all exceptions being masked), so to be
consistent set the same environment also when using xsave. This is
also in line with all SSE exceptions getting masked initially.

To avoid further fragile casts in xstate_alloc_save_area() the patch
also changes xsave_struct's fpu_see member to have actually usable
fields.

The patch was tested in its technically identical, but modified-file-
wise different 4.1.2 version.

Signed-off-by: Jan Beulich <jbeulich@xxxxxxxx>
Tested-by: Charles Arnold <carnold@xxxxxxxx>

--- a/xen/arch/x86/i387.c
+++ b/xen/arch/x86/i387.c
@@ -17,7 +17,6 @@
 #include <asm/xstate.h>
 #include <asm/asm_defns.h>
 
-#define MXCSR_DEFAULT 0x1f80
 static void fpu_init(void)
 {
     unsigned long val;
--- a/xen/arch/x86/xstate.c
+++ b/xen/arch/x86/xstate.c
@@ -97,7 +97,7 @@ bool_t xsave_enabled(const struct vcpu *
 
 int xstate_alloc_save_area(struct vcpu *v)
 {
-    void *save_area;
+    struct xsave_struct *save_area;
 
     if ( !cpu_has_xsave || is_idle_vcpu(v) )
         return 0;
@@ -109,8 +109,9 @@ int xstate_alloc_save_area(struct vcpu *
     if ( save_area == NULL )
         return -ENOMEM;
 
-    ((u32 *)save_area)[6] = 0x1f80;  /* MXCSR */
-    *(uint64_t *)(save_area + 512) = XSTATE_FP_SSE;  /* XSETBV */
+    save_area->fpu_sse.fcw = FCW_DEFAULT;
+    save_area->fpu_sse.mxcsr = MXCSR_DEFAULT;
+    save_area->xsave_hdr.xstate_bv = XSTATE_FP_SSE;
 
     v->arch.xsave_area = save_area;
     v->arch.xcr0 = XSTATE_FP_SSE;
--- a/xen/include/asm-x86/xstate.h
+++ b/xen/include/asm-x86/xstate.h
@@ -11,6 +11,9 @@
 #include <xen/types.h>
 #include <xen/percpu.h>
 
+#define FCW_DEFAULT               0x037f
+#define MXCSR_DEFAULT             0x1f80
+
 #define XSTATE_CPUID              0x0000000d
 #define XSTATE_FEATURE_XSAVEOPT   (1 << 0)    /* sub-leaf 1, eax[bit 0] */
 
@@ -46,7 +49,29 @@ extern u64 xfeature_mask;
 /* extended state save area */
 struct xsave_struct
 {
-    struct { char x[512]; } fpu_sse;         /* FPU/MMX, SSE */
+    union {                                  /* FPU/MMX, SSE */
+        char x[512];
+        struct {
+            uint16_t fcw;
+            uint16_t fsw;
+            uint8_t ftw;
+            uint8_t rsvd1;
+            uint16_t fop;
+            union {
+#ifdef __x86_64__
+                uint64_t addr;
+#endif
+                struct {
+                    uint32_t offs;
+                    uint16_t sel;
+                    uint16_t rsvd;
+                };
+            } fip, fdp;
+            uint32_t mxcsr;
+            uint32_t mxcsr_mask;
+            /* data registers follow here */
+        };
+    } fpu_sse;
 
     struct {
         u64 xstate_bv;