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[Date Prev][Date Next][Thread Prev][Thread Next][Date Index][Thread Index] [Xen-devel] Re: [Qemu-devel] [PATCH V3 07/10] Introduce Xen PCI Passthrough, qdevice (1/3)
On Tue, Nov 8, 2011 at 12:56, Stefano Stabellini
<stefano.stabellini@xxxxxxxxxxxxx> wrote:
> On Fri, 28 Oct 2011, Anthony PERARD wrote:
>> From: Allen Kay <allen.m.kay@xxxxxxxxx>
>>
>> Signed-off-by: Allen Kay <allen.m.kay@xxxxxxxxx>
>> Signed-off-by: Guy Zana <guy@xxxxxxxxxxxx>
>> Signed-off-by: Anthony PERARD <anthony.perard@xxxxxxxxxx>
>> ---
>> ÂMakefile.target         Â|  Â2 +
>> Âhw/xen_pci_passthrough.c     | Â838
>> ++++++++++++++++++++++++++++++++++++++
>> Âhw/xen_pci_passthrough.h     | Â223 ++++++++++
>> Âhw/xen_pci_passthrough_helpers.c | Â 46 ++
>> Â4 files changed, 1109 insertions(+), 0 deletions(-)
>> Âcreate mode 100644 hw/xen_pci_passthrough.c
>> Âcreate mode 100644 hw/xen_pci_passthrough.h
>> Âcreate mode 100644 hw/xen_pci_passthrough_helpers.c
>>
>> diff --git a/Makefile.target b/Makefile.target
>> index 243f9f2..36ea47d 100644
>> --- a/Makefile.target
>> +++ b/Makefile.target
>> @@ -217,6 +217,8 @@ obj-i386-$(CONFIG_XEN) += xen_platform.o
>>
>> Â# Xen PCI Passthrough
>> Âobj-i386-$(CONFIG_XEN_PCI_PASSTHROUGH) += host-pci-device.o
>> +obj-i386-$(CONFIG_XEN_PCI_PASSTHROUGH) += xen_pci_passthrough.o
>> +obj-i386-$(CONFIG_XEN_PCI_PASSTHROUGH) += xen_pci_passthrough_helpers.o
>>
>> Â# Inter-VM PCI shared memory
>> ÂCONFIG_IVSHMEM =
>> diff --git a/hw/xen_pci_passthrough.c b/hw/xen_pci_passthrough.c
>> new file mode 100644
>> index 0000000..b97c5b6
>> --- /dev/null
>> +++ b/hw/xen_pci_passthrough.c
>> @@ -0,0 +1,838 @@
>> +/*
>> + * Copyright (c) 2007, Neocleus Corporation.
>> + * Copyright (c) 2007, Intel Corporation.
>> + *
>> + * This work is licensed under the terms of the GNU GPL, version 2. ÂSee
>> + * the COPYING file in the top-level directory.
>> + *
>> + * Alex Novik <alex@xxxxxxxxxxxx>
>> + * Allen Kay <allen.m.kay@xxxxxxxxx>
>> + * Guy Zana <guy@xxxxxxxxxxxx>
>> + *
>> + * This file implements direct PCI assignment to a HVM guest
>> + */
>> +
>> +/*
>> + * Interrupt Disable policy:
>> + *
>> + * INTx interrupt:
>> + * Â Initialize(register_real_device)
>> + * Â Â Map INTx(xc_physdev_map_pirq):
>> + * Â Â Â <fail>
>> + * Â Â Â Â - Set real Interrupt Disable bit to '1'.
>> + * Â Â Â Â - Set machine_irq and assigned_device->machine_irq to '0'.
>> + * Â Â Â Â * Don't bind INTx.
>> + *
>> + * Â Â Bind INTx(xc_domain_bind_pt_pci_irq):
>> + * Â Â Â <fail>
>> + * Â Â Â Â - Set real Interrupt Disable bit to '1'.
>> + * Â Â Â Â - Unmap INTx.
>> + * Â Â Â Â - Decrement mapped_machine_irq[machine_irq]
>> + * Â Â Â Â - Set assigned_device->machine_irq to '0'.
>> + *
>> + * Â Write to Interrupt Disable bit by guest software(pt_cmd_reg_write)
>> + * Â Â Write '0'
>> + * Â Â Â <ptdev->msi_trans_en is false>
>> + * Â Â Â Â - Set real bit to '0' if assigned_device->machine_irq isn't '0'.
>> + *
>> + * Â Â Write '1'
>> + * Â Â Â <ptdev->msi_trans_en is false>
>> + * Â Â Â Â - Set real bit to '1'.
>> + *
>> + * MSI-INTx translation.
>> + * Â Initialize(xc_physdev_map_pirq_msi/pt_msi_setup)
>> + * Â Â Bind MSI-INTx(xc_domain_bind_pt_irq)
>> + * Â Â Â <fail>
>> + * Â Â Â Â - Unmap MSI.
>> + * Â Â Â Â Â <success>
>> + * Â Â Â Â Â Â - Set dev->msi->pirq to '-1'.
>> + * Â Â Â Â Â <fail>
>> + * Â Â Â Â Â Â - Do nothing.
>> + *
>> + * Â Write to Interrupt Disable bit by guest software(pt_cmd_reg_write)
>> + * Â Â Write '0'
>> + * Â Â Â <ptdev->msi_trans_en is true>
>> + * Â Â Â Â - Set MSI Enable bit to '1'.
>> + *
>> + * Â Â Write '1'
>> + * Â Â Â <ptdev->msi_trans_en is true>
>> + * Â Â Â Â - Set MSI Enable bit to '0'.
>> + *
>> + * MSI interrupt:
>> + * Â Initialize MSI register(pt_msi_setup, pt_msi_update)
>> + * Â Â Bind MSI(xc_domain_update_msi_irq)
>> + * Â Â Â <fail>
>> + * Â Â Â Â - Unmap MSI.
>> + * Â Â Â Â - Set dev->msi->pirq to '-1'.
>> + *
>> + * MSI-X interrupt:
>> + * Â Initialize MSI-X register(pt_msix_update_one)
>> + * Â Â Bind MSI-X(xc_domain_update_msi_irq)
>> + * Â Â Â <fail>
>> + * Â Â Â Â - Unmap MSI-X.
>> + * Â Â Â Â - Set entry->pirq to '-1'.
>> + */
>> +
>
> you should move all the MSI related comments to the MSI patch
OK, I will move MSI comments.
>> +#include <sys/ioctl.h>
>> +
>> +#include "pci.h"
>> +#include "xen.h"
>> +#include "xen_backend.h"
>> +#include "xen_pci_passthrough.h"
>> +
>> +#define PCI_BAR_ENTRIES (6)
>> +
>> +#define PT_NR_IRQS Â Â Â Â Â(256)
>> +char mapped_machine_irq[PT_NR_IRQS] = {0};
>> +
>> +/* Config Space */
>> +static int pt_pci_config_access_check(PCIDevice *d, uint32_t address, int
>> len)
>> +{
>> + Â Â/* check offset range */
>> + Â Âif (address >= 0xFF) {
>> + Â Â Â ÂPT_LOG("Error: Failed to access register with offset exceeding FFh.
>> "
>> + Â Â Â Â Â Â Â "[%02x:%02x.%x][Offset:%02xh][Length:%d]\n",
>> + Â Â Â Â Â Â Â pci_bus_num(d->bus), PCI_SLOT(d->devfn), PCI_FUNC(d->devfn),
>> + Â Â Â Â Â Â Â address, len);
>> + Â Â Â Âreturn -1;
>> + Â Â}
>> +
>> + Â Â/* check read size */
>> + Â Âif ((len != 1) && (len != 2) && (len != 4)) {
>> + Â Â Â ÂPT_LOG("Error: Failed to access register with invalid access
>> length. "
>> + Â Â Â Â Â Â Â "[%02x:%02x.%x][Offset:%02xh][Length:%d]\n",
>> + Â Â Â Â Â Â Â pci_bus_num(d->bus), PCI_SLOT(d->devfn), PCI_FUNC(d->devfn),
>> + Â Â Â Â Â Â Â address, len);
>> + Â Â Â Âreturn -1;
>> + Â Â}
>> +
>> + Â Â/* check offset alignment */
>> + Â Âif (address & (len - 1)) {
>> + Â Â Â ÂPT_LOG("Error: Failed to access register with invalid access size "
>> + Â Â Â Â Â Â"alignment. [%02x:%02x.%x][Offset:%02xh][Length:%d]\n",
>> + Â Â Â Â Â Âpci_bus_num(d->bus), PCI_SLOT(d->devfn), PCI_FUNC(d->devfn),
>> + Â Â Â Â Â Âaddress, len);
>> + Â Â Â Âreturn -1;
>> + Â Â}
>> +
>> + Â Âreturn 0;
>> +}
>> +
>> +int pt_bar_offset_to_index(uint32_t offset)
>> +{
>> + Â Âint index = 0;
>> +
>> + Â Â/* check Exp ROM BAR */
>> + Â Âif (offset == PCI_ROM_ADDRESS) {
>> + Â Â Â Âreturn PCI_ROM_SLOT;
>> + Â Â}
>> +
>> + Â Â/* calculate BAR index */
>> + Â Âindex = (offset - PCI_BASE_ADDRESS_0) >> 2;
>> + Â Âif (index >= PCI_NUM_REGIONS) {
>> + Â Â Â Âreturn -1;
>> + Â Â}
>> +
>> + Â Âreturn index;
>> +}
>> +
>> +static uint32_t pt_pci_read_config(PCIDevice *d, uint32_t address, int len)
>> +{
>> + Â ÂXenPCIPassthroughState *s = DO_UPCAST(XenPCIPassthroughState, dev, d);
>> + Â Âuint32_t val = 0;
>> + Â ÂXenPTRegGroup *reg_grp_entry = NULL;
>> + Â ÂXenPTReg *reg_entry = NULL;
>> + Â Âint rc = 0;
>> + Â Âint emul_len = 0;
>> + Â Âuint32_t find_addr = address;
>> +
>> + Â Âif (pt_pci_config_access_check(d, address, len)) {
>> + Â Â Â Âgoto exit;
>> + Â Â}
>> +
>> + Â Â/* check power state transition flags */
>> + Â Âif (s->pm_state != NULL && s->pm_state->flags & PT_FLAG_TRANSITING) {
>> + Â Â Â Â/* can't accept until previous power state transition is completed.
>> + Â Â Â Â * so finished previous request here.
>> + Â Â Â Â */
>> + Â Â Â ÂPT_LOG("Warning: guest want to write durring power state
>> transition\n");
>> + Â Â Â Âgoto exit;
>> + Â Â}
>> +
>> + Â Â/* find register group entry */
>> + Â Âreg_grp_entry = pt_find_reg_grp(s, address);
>> + Â Âif (reg_grp_entry) {
>> + Â Â Â Â/* check 0 Hardwired register group */
>> + Â Â Â Âif (reg_grp_entry->reg_grp->grp_type == GRP_TYPE_HARDWIRED) {
>> + Â Â Â Â Â Â/* no need to emulate, just return 0 */
>> + Â Â Â Â Â Âval = 0;
>> + Â Â Â Â Â Âgoto exit;
>> + Â Â Â Â}
>> + Â Â}
>> +
>> + Â Â/* read I/O device register value */
>> + Â Ârc = host_pci_get_block(s->real_device, address, (uint8_t *)&val, len);
>> + Â Âif (!rc) {
>> + Â Â Â ÂPT_LOG("Error: pci_read_block failed. return value[%d].\n", rc);
>> + Â Â Â Âmemset(&val, 0xff, len);
>> + Â Â}
>> +
>> + Â Â/* just return the I/O device register value for
>> + Â Â * passthrough type register group */
>> + Â Âif (reg_grp_entry == NULL) {
>> + Â Â Â Âgoto exit;
>> + Â Â}
>> +
>> + Â Â/* adjust the read value to appropriate CFC-CFF window */
>> + Â Âval <<= (address & 3) << 3;
>> + Â Âemul_len = len;
>> +
>> + Â Â/* loop Guest request size */
>> + Â Âwhile (emul_len > 0) {
>> + Â Â Â Â/* find register entry to be emulated */
>> + Â Â Â Âreg_entry = pt_find_reg(reg_grp_entry, find_addr);
>> + Â Â Â Âif (reg_entry) {
>> + Â Â Â Â Â ÂXenPTRegInfo *reg = reg_entry->reg;
>> + Â Â Â Â Â Âuint32_t real_offset = reg_grp_entry->base_offset + reg->offset;
>> + Â Â Â Â Â Âuint32_t valid_mask = 0xFFFFFFFF >> ((4 - emul_len) << 3);
>> + Â Â Â Â Â Âuint8_t *ptr_val = NULL;
>> +
>> + Â Â Â Â Â Âvalid_mask <<= (find_addr - real_offset) << 3;
>> + Â Â Â Â Â Âptr_val = (uint8_t *)&val + (real_offset & 3);
>> +
>> + Â Â Â Â Â Â/* do emulation depend on register size */
>> + Â Â Â Â Â Âswitch (reg->size) {
>> + Â Â Â Â Â Âcase 1:
>> + Â Â Â Â Â Â Â Âif (reg->u.b.read) {
>> + Â Â Â Â Â Â Â Â Â Ârc = reg->u.b.read(s, reg_entry, ptr_val, valid_mask);
>> + Â Â Â Â Â Â Â Â}
>> + Â Â Â Â Â Â Â Âbreak;
>> + Â Â Â Â Â Âcase 2:
>> + Â Â Â Â Â Â Â Âif (reg->u.w.read) {
>> + Â Â Â Â Â Â Â Â Â Ârc = reg->u.w.read(s, reg_entry,
>> + Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â (uint16_t *)ptr_val, valid_mask);
>> + Â Â Â Â Â Â Â Â}
>> + Â Â Â Â Â Â Â Âbreak;
>> + Â Â Â Â Â Âcase 4:
>> + Â Â Â Â Â Â Â Âif (reg->u.dw.read) {
>> + Â Â Â Â Â Â Â Â Â Ârc = reg->u.dw.read(s, reg_entry,
>> + Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â(uint32_t *)ptr_val, valid_mask);
>> + Â Â Â Â Â Â Â Â}
>> + Â Â Â Â Â Â Â Âbreak;
>> + Â Â Â Â Â Â}
>> +
>> + Â Â Â Â Â Âif (rc < 0) {
>> + Â Â Â Â Â Â Â Âhw_error("Internal error: Invalid read emulation "
>> + Â Â Â Â Â Â Â Â Â Â Â Â "return value[%d]. I/O emulator exit.\n", rc);
>> + Â Â Â Â Â Â}
>> +
>> + Â Â Â Â Â Â/* calculate next address to find */
>> + Â Â Â Â Â Âemul_len -= reg->size;
>> + Â Â Â Â Â Âif (emul_len > 0) {
>> + Â Â Â Â Â Â Â Âfind_addr = real_offset + reg->size;
>> + Â Â Â Â Â Â}
>> + Â Â Â Â} else {
>> + Â Â Â Â Â Â/* nothing to do with passthrough type register,
>> + Â Â Â Â Â Â * continue to find next byte */
>> + Â Â Â Â Â Âemul_len--;
>> + Â Â Â Â Â Âfind_addr++;
>> + Â Â Â Â}
>> + Â Â}
>> +
>> + Â Â/* need to shift back before returning them to pci bus emulator */
>> + Â Âval >>= ((address & 3) << 3);
>> +
>> +exit:
>> + Â ÂPT_LOG_CONFIG("[%02x:%02x.%x]: address=%04x val=0x%08x len=%d\n",
>> + Â Â Â Â Â Â Â Â Âpci_bus_num(d->bus), PCI_SLOT(d->devfn),
>> PCI_FUNC(d->devfn),
>> + Â Â Â Â Â Â Â Â Âaddress, val, len);
>> + Â Âreturn val;
>> +}
>> +
>> +static void pt_pci_write_config(PCIDevice *d, uint32_t address,
>> + Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â Âuint32_t val, int len)
>> +{
>> + Â ÂXenPCIPassthroughState *s = DO_UPCAST(XenPCIPassthroughState, dev, d);
>> + Â Âint index = 0;
>> + Â ÂXenPTRegGroup *reg_grp_entry = NULL;
>> + Â Âint rc = 0;
>> + Â Âuint32_t read_val = 0;
>> + Â Âint emul_len = 0;
>> + Â ÂXenPTReg *reg_entry = NULL;
>> + Â Âuint32_t find_addr = address;
>> + Â ÂXenPTRegInfo *reg = NULL;
>> +
>> + Â Âif (pt_pci_config_access_check(d, address, len)) {
>> + Â Â Â Âreturn;
>> + Â Â}
>> +
>> + Â ÂPT_LOG_CONFIG("[%02x:%02x.%x]: address=%04x val=0x%08x len=%d\n",
>> + Â Â Â Â Â Â Â Â Âpci_bus_num(d->bus), PCI_SLOT(d->devfn),
>> PCI_FUNC(d->devfn),
>> + Â Â Â Â Â Â Â Â Âaddress, val, len);
>> +
>> + Â Â/* check unused BAR register */
>> + Â Âindex = pt_bar_offset_to_index(address);
>> + Â Âif ((index >= 0) && (val > 0 && val < PT_BAR_ALLF) &&
>> + Â Â Â Â(s->bases[index].bar_flag == PT_BAR_FLAG_UNUSED)) {
>> + Â Â Â ÂPT_LOG("Warning: Guest attempt to set address to unused Base
>> Address "
>> + Â Â Â Â Â Â Â "Register. [%02x:%02x.%x][Offset:%02xh][Length:%d]\n",
>> + Â Â Â Â Â Â Â pci_bus_num(d->bus), PCI_SLOT(d->devfn), PCI_FUNC(d->devfn),
>> + Â Â Â Â Â Â Â address, len);
>> + Â Â}
>> +
>> + Â Â/* check power state transition flags */
>> + Â Âif (s->pm_state != NULL && s->pm_state->flags & PT_FLAG_TRANSITING) {
>> + Â Â Â Â/* can't accept untill previous power state transition is completed.
>> + Â Â Â Â * so finished previous request here.
>> + Â Â Â Â */
>> + Â Â Â ÂPT_LOG("Warning: guest want to write durring power state
>> transition\n");
>> + Â Â Â Âreturn;
>> + Â Â}
>> +
>> + Â Â/* find register group entry */
>> + Â Âreg_grp_entry = pt_find_reg_grp(s, address);
>> + Â Âif (reg_grp_entry) {
>> + Â Â Â Â/* check 0 Hardwired register group */
>> + Â Â Â Âif (reg_grp_entry->reg_grp->grp_type == GRP_TYPE_HARDWIRED) {
>> + Â Â Â Â Â Â/* ignore silently */
>> + Â Â Â Â Â ÂPT_LOG("Warning: Access to 0 Hardwired register. "
>> + Â Â Â Â Â Â Â Â Â "[%02x:%02x.%x][Offset:%02xh][Length:%d]\n",
>> + Â Â Â Â Â Â Â Â Â pci_bus_num(d->bus), PCI_SLOT(d->devfn),
>> PCI_FUNC(d->devfn),
>> + Â Â Â Â Â Â Â Â Â address, len);
>> + Â Â Â Â Â Âreturn;
>> + Â Â Â Â}
>> + Â Â}
>> +
>> + Â Â/* read I/O device register value */
>> + Â Ârc = host_pci_get_block(s->real_device, address,
>> + Â Â Â Â Â Â Â Â Â Â Â Â Â Â (uint8_t *)&read_val, len);
>> + Â Âif (!rc) {
>> + Â Â Â ÂPT_LOG("Error: pci_read_block failed. return value[%d].\n", rc);
>> + Â Â Â Âmemset(&read_val, 0xff, len);
>> + Â Â}
>> +
>> + Â Â/* pass directly to libpci for passthrough type register group */
>> + Â Âif (reg_grp_entry == NULL) {
>> + Â Â Â Âgoto out;
>> + Â Â}
>> +
>> + Â Â/* adjust the read and write value to appropriate CFC-CFF window */
>> + Â Âread_val <<= (address & 3) << 3;
>> + Â Âval <<= (address & 3) << 3;
>> + Â Âemul_len = len;
>> +
>> + Â Â/* loop Guest request size */
>> + Â Âwhile (emul_len > 0) {
>> + Â Â Â Â/* find register entry to be emulated */
>> + Â Â Â Âreg_entry = pt_find_reg(reg_grp_entry, find_addr);
>> + Â Â Â Âif (reg_entry) {
>> + Â Â Â Â Â Âreg = reg_entry->reg;
>> + Â Â Â Â Â Âuint32_t real_offset = reg_grp_entry->base_offset + reg->offset;
>> + Â Â Â Â Â Âuint32_t valid_mask = 0xFFFFFFFF >> ((4 - emul_len) << 3);
>> + Â Â Â Â Â Âuint8_t *ptr_val = NULL;
>> +
>> + Â Â Â Â Â Âvalid_mask <<= (find_addr - real_offset) << 3;
>> + Â Â Â Â Â Âptr_val = (uint8_t *)&val + (real_offset & 3);
>> +
>> + Â Â Â Â Â Â/* do emulation depend on register size */
>> + Â Â Â Â Â Âswitch (reg->size) {
>> + Â Â Â Â Â Âcase 1:
>> + Â Â Â Â Â Â Â Âif (reg->u.b.write) {
>> + Â Â Â Â Â Â Â Â Â Ârc = reg->u.b.write(s, reg_entry, ptr_val,
>> + Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â Âread_val >> ((real_offset & 3) <<
>> 3),
>> + Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â Âvalid_mask);
>> + Â Â Â Â Â Â Â Â}
>> + Â Â Â Â Â Â Â Âbreak;
>> + Â Â Â Â Â Âcase 2:
>> + Â Â Â Â Â Â Â Âif (reg->u.w.write) {
>> + Â Â Â Â Â Â Â Â Â Ârc = reg->u.w.write(s, reg_entry, (uint16_t *)ptr_val,
>> + Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â(read_val >> ((real_offset & 3) <<
>> 3)),
>> + Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â Âvalid_mask);
>> + Â Â Â Â Â Â Â Â}
>> + Â Â Â Â Â Â Â Âbreak;
>> + Â Â Â Â Â Âcase 4:
>> + Â Â Â Â Â Â Â Âif (reg->u.dw.write) {
>> + Â Â Â Â Â Â Â Â Â Ârc = reg->u.dw.write(s, reg_entry, (uint32_t *)ptr_val,
>> + Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â (read_val >> ((real_offset & 3) <<
>> 3)),
>> + Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â valid_mask);
>> + Â Â Â Â Â Â Â Â}
>> + Â Â Â Â Â Â Â Âbreak;
>> + Â Â Â Â Â Â}
>> +
>> + Â Â Â Â Â Âif (rc < 0) {
>> + Â Â Â Â Â Â Â Âhw_error("Internal error: Invalid write emulation "
>> + Â Â Â Â Â Â Â Â Â Â Â Â "return value[%d]. I/O emulator exit.\n", rc);
>> + Â Â Â Â Â Â}
>> +
>> + Â Â Â Â Â Â/* calculate next address to find */
>> + Â Â Â Â Â Âemul_len -= reg->size;
>> + Â Â Â Â Â Âif (emul_len > 0) {
>> + Â Â Â Â Â Â Â Âfind_addr = real_offset + reg->size;
>> + Â Â Â Â Â Â}
>> + Â Â Â Â} else {
>> + Â Â Â Â Â Â/* nothing to do with passthrough type register,
>> + Â Â Â Â Â Â * continue to find next byte */
>> + Â Â Â Â Â Âemul_len--;
>> + Â Â Â Â Â Âfind_addr++;
>> + Â Â Â Â}
>> + Â Â}
>> +
>> + Â Â/* need to shift back before passing them to libpci */
>> + Â Âval >>= (address & 3) << 3;
>> +
>> +out:
>> + Â Âif (!(reg && reg->no_wb)) {
>> + Â Â Â Â/* unknown regs are passed through */
>> + Â Â Â Ârc = host_pci_set_block(s->real_device, address, (uint8_t *)&val,
>> len);
>> +
>> + Â Â Â Âif (!rc) {
>> + Â Â Â Â Â ÂPT_LOG("Error: pci_write_block failed. return value[%d].\n",
>> rc);
>> + Â Â Â Â}
>> + Â Â}
>> +
>> + Â Âif (s->pm_state != NULL && s->pm_state->flags & PT_FLAG_TRANSITING) {
>> + Â Â Â Âqemu_mod_timer(s->pm_state->pm_timer,
>> + Â Â Â Â Â Â Â Â Â Â Â qemu_get_clock_ms(rt_clock) + s->pm_state->pm_delay);
>> + Â Â}
>> +}
>
> Where is this timer allocated and initialized?
In the next patch, I will move this lines to the releated patch.
>> +/* ioport/iomem space*/
>> +static void pt_iomem_map(XenPCIPassthroughState *s, int i,
>> + Â Â Â Â Â Â Â Â Â Â Â Â pcibus_t e_phys, pcibus_t e_size, int type)
>> +{
>> + Â Âuint32_t old_ebase = s->bases[i].e_physbase;
>> + Â Âbool first_map = s->bases[i].e_size == 0;
>> + Â Âint ret = 0;
>> +
>> + Â Âs->bases[i].e_physbase = e_phys;
>> + Â Âs->bases[i].e_size = e_size;
>> +
>> + Â ÂPT_LOG("e_phys=%#"PRIx64" maddr=%#"PRIx64" type=%%d"
>> + Â Â Â Â Â " len=%#"PRIx64" index=%d first_map=%d\n",
>> + Â Â Â Â Â e_phys, s->bases[i].access.maddr, /*type,*/
>> + Â Â Â Â Â e_size, i, first_map);
>> +
>> + Â Âif (e_size == 0) {
>> + Â Â Â Âreturn;
>> + Â Â}
>> +
>> + Â Âif (!first_map && old_ebase != -1) {
>> + Â Â Â Â/* Remove old mapping */
>> + Â Â Â Âret = xc_domain_memory_mapping(xen_xc, xen_domid,
>> + Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â old_ebase >> XC_PAGE_SHIFT,
>> + Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â s->bases[i].access.maddr >> XC_PAGE_SHIFT,
>> + Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â (e_size + XC_PAGE_SIZE - 1) >> XC_PAGE_SHIFT,
>> + Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â DPCI_REMOVE_MAPPING);
>> + Â Â Â Âif (ret != 0) {
>> + Â Â Â Â Â ÂPT_LOG("Error: remove old mapping failed!\n");
>> + Â Â Â Â Â Âreturn;
>> + Â Â Â Â}
>> + Â Â}
>> +
>> + Â Â/* map only valid guest address */
>> + Â Âif (e_phys != -1) {
>> + Â Â Â Â/* Create new mapping */
>> + Â Â Â Âret = xc_domain_memory_mapping(xen_xc, xen_domid,
>> + Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â s->bases[i].e_physbase >> XC_PAGE_SHIFT,
>> + Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â s->bases[i].access.maddr >>
>> XC_PAGE_SHIFT,
>> + Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â (e_size+XC_PAGE_SIZE-1) >> XC_PAGE_SHIFT,
>> + Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â DPCI_ADD_MAPPING);
>> +
>> + Â Â Â Âif (ret != 0) {
>> + Â Â Â Â Â ÂPT_LOG("Error: create new mapping failed!\n");
>> + Â Â Â Â}
>> + Â Â}
>> +}
>> +
>> +static void pt_ioport_map(XenPCIPassthroughState *s, int i,
>> + Â Â Â Â Â Â Â Â Â Â Â Â Âpcibus_t e_phys, pcibus_t e_size, int type)
>> +{
>> + Â Âuint32_t old_ebase = s->bases[i].e_physbase;
>> + Â Âbool first_map = s->bases[i].e_size == 0;
>> + Â Âint ret = 0;
>> +
>> + Â Âs->bases[i].e_physbase = e_phys;
>> + Â Âs->bases[i].e_size = e_size;
>> +
>> + Â ÂPT_LOG("e_phys=%#04"PRIx64" pio_base=%#04"PRIx64" len=%"PRId64"
>> index=%d"
>> + Â Â Â Â Â " first_map=%d\n",
>> + Â Â Â Â Â e_phys, s->bases[i].access.pio_base, e_size, i, first_map);
>> +
>> + Â Âif (e_size == 0) {
>> + Â Â Â Âreturn;
>> + Â Â}
>> +
>> + Â Âif (!first_map && old_ebase != -1) {
>> + Â Â Â Â/* Remove old mapping */
>> + Â Â Â Âret = xc_domain_ioport_mapping(xen_xc, xen_domid, old_ebase,
>> + Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â s->bases[i].access.pio_base, e_size,
>> + Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â DPCI_REMOVE_MAPPING);
>> + Â Â Â Âif (ret != 0) {
>> + Â Â Â Â Â ÂPT_LOG("Error: remove old mapping failed!\n");
>> + Â Â Â Â Â Âreturn;
>> + Â Â Â Â}
>> + Â Â}
>> +
>> + Â Â/* map only valid guest address (include 0) */
>> + Â Âif (e_phys != -1) {
>> + Â Â Â Â/* Create new mapping */
>> + Â Â Â Âret = xc_domain_ioport_mapping(xen_xc, xen_domid, e_phys,
>> + Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â s->bases[i].access.pio_base, e_size,
>> + Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â DPCI_ADD_MAPPING);
>> + Â Â Â Âif (ret != 0) {
>> + Â Â Â Â Â ÂPT_LOG("Error: create new mapping failed!\n");
>> + Â Â Â Â}
>> + Â Â}
>> +
>> +}
>> +
>> +
>> +/* mapping BAR */
>> +
>> +void pt_bar_mapping_one(XenPCIPassthroughState *s, int bar,
>> + Â Â Â Â Â Â Â Â Â Â Â Âint io_enable, int mem_enable)
>> +{
>> + Â ÂPCIDevice *dev = &s->dev;
>> + Â ÂPCIIORegion *r;
>> + Â ÂXenPTRegGroup *reg_grp_entry = NULL;
>> + Â ÂXenPTReg *reg_entry = NULL;
>> + Â ÂXenPTRegion *base = NULL;
>> + Â Âpcibus_t r_size = 0, r_addr = -1;
>> + Â Âint rc = 0;
>> +
>> + Â Âr = &dev->io_regions[bar];
>> +
>> + Â Â/* check valid region */
>> + Â Âif (!r->size) {
>> + Â Â Â Âreturn;
>> + Â Â}
>> +
>> + Â Âbase = &s->bases[bar];
>> + Â Â/* skip unused BAR or upper 64bit BAR */
>> + Â Âif ((base->bar_flag == PT_BAR_FLAG_UNUSED)
>> + Â Â Â Â|| (base->bar_flag == PT_BAR_FLAG_UPPER)) {
>> + Â Â Â Â Â return;
>> + Â Â}
>> +
>> + Â Â/* copy region address to temporary */
>> + Â Âr_addr = r->addr;
>> +
>> + Â Â/* need unmapping in case I/O Space or Memory Space disable */
>> + Â Âif (((base->bar_flag == PT_BAR_FLAG_IO) && !io_enable) ||
>> + Â Â Â Â((base->bar_flag == PT_BAR_FLAG_MEM) && !mem_enable)) {
>> + Â Â Â Âr_addr = -1;
>> + Â Â}
>> + Â Âif ((bar == PCI_ROM_SLOT) && (r_addr != -1)) {
>> + Â Â Â Âreg_grp_entry = pt_find_reg_grp(s, PCI_ROM_ADDRESS);
>> + Â Â Â Âif (reg_grp_entry) {
>> + Â Â Â Â Â Âreg_entry = pt_find_reg(reg_grp_entry, PCI_ROM_ADDRESS);
>> + Â Â Â Â Â Âif (reg_entry && !(reg_entry->data & PCI_ROM_ADDRESS_ENABLE)) {
>> + Â Â Â Â Â Â Â Âr_addr = -1;
>> + Â Â Â Â Â Â}
>> + Â Â Â Â}
>> + Â Â}
>> +
>> + Â Â/* prevent guest software mapping memory resource to 00000000h */
>> + Â Âif ((base->bar_flag == PT_BAR_FLAG_MEM) && (r_addr == 0)) {
>> + Â Â Â Âr_addr = -1;
>> + Â Â}
>> +
>> + Â Âr_size = pt_get_emul_size(base->bar_flag, r->size);
>> +
>> + Â Ârc = pci_check_bar_overlap(dev, r_addr, r_size, r->type);
>> + Â Âif (rc > 0) {
>> + Â Â Â ÂPT_LOG("Warning: s[%02x:%02x.%x][Region:%d][Address:%"FMT_PCIBUS"h]"
>> + Â Â Â Â Â Â Â "[Size:%"FMT_PCIBUS"h] is overlapped.\n",
>> pci_bus_num(dev->bus),
>> + Â Â Â Â Â Â Â PCI_SLOT(dev->devfn), PCI_FUNC(dev->devfn), bar,
>> + Â Â Â Â Â Â Â r_addr, r_size);
>> + Â Â}
>> +
>> + Â Â/* check whether we need to update the mapping or not */
>> + Â Âif (r_addr != s->bases[bar].e_physbase) {
>> + Â Â Â Â/* mapping BAR */
>> + Â Â Â Âif (base->bar_flag == PT_BAR_FLAG_IO) {
>> + Â Â Â Â Â Âpt_ioport_map(s, bar, r_addr, r_size, r->type);
>> + Â Â Â Â} else {
>> + Â Â Â Â Â Âpt_iomem_map(s, bar, r_addr, r_size, r->type);
>> + Â Â Â Â}
>> + Â Â}
>> +}
>> +
>> +void pt_bar_mapping(XenPCIPassthroughState *s, int io_enable, int
>> mem_enable)
>> +{
>> + Â Âint i;
>> +
>> + Â Âfor (i = 0; i < PCI_NUM_REGIONS; i++) {
>> + Â Â Â Âpt_bar_mapping_one(s, i, io_enable, mem_enable);
>> + Â Â}
>> +}
>> +
>> +/* register regions */
>> +static int pt_register_regions(XenPCIPassthroughState *s)
>> +{
>> + Â Âint i = 0;
>> + Â Âuint32_t bar_data = 0;
>> + Â ÂHostPCIDevice *d = s->real_device;
>> +
>> + Â Â/* Register PIO/MMIO BARs */
>> + Â Âfor (i = 0; i < PCI_BAR_ENTRIES; i++) {
>> + Â Â Â ÂHostPCIIORegion *r = &d->io_regions[i];
>> +
>> + Â Â Â Âif (r->base_addr) {
>> + Â Â Â Â Â Âs->bases[i].e_physbase = r->base_addr;
>> + Â Â Â Â Â Âs->bases[i].access.u = r->base_addr;
>> +
>> + Â Â Â Â Â Â/* Register current region */
>> + Â Â Â Â Â Âif (r->flags & IORESOURCE_IO) {
>> + Â Â Â Â Â Â Â Âmemory_region_init_io(&s->bar[i], NULL, NULL,
>> + Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â"xen-pci-pt-bar", r->size);
>> + Â Â Â Â Â Â Â Âpci_register_bar(&s->dev, i, PCI_BASE_ADDRESS_SPACE_IO,
>> + Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â &s->bar[i]);
>> + Â Â Â Â Â Â} else if (r->flags & IORESOURCE_PREFETCH) {
>> + Â Â Â Â Â Â Â Âmemory_region_init_io(&s->bar[i], NULL, NULL,
>> + Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â"xen-pci-pt-bar", r->size);
>> + Â Â Â Â Â Â Â Âpci_register_bar(&s->dev, i, PCI_BASE_ADDRESS_MEM_PREFETCH,
>> + Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â &s->bar[i]);
>> + Â Â Â Â Â Â} else {
>> + Â Â Â Â Â Â Â Âmemory_region_init_io(&s->bar[i], NULL, NULL,
>> + Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â"xen-pci-pt-bar", r->size);
>> + Â Â Â Â Â Â Â Âpci_register_bar(&s->dev, i, PCI_BASE_ADDRESS_SPACE_MEMORY,
>> + Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â &s->bar[i]);
>> + Â Â Â Â Â Â}
>> +
>> + Â Â Â Â Â ÂPT_LOG("IO region registered (size=0x%08"PRIx64
>> + Â Â Â Â Â Â Â Â Â " base_addr=0x%08"PRIx64")\n",
>> + Â Â Â Â Â Â Â Â Â r->size, r->base_addr);
>> + Â Â Â Â}
>> + Â Â}
>> +
>> + Â Â/* Register expansion ROM address */
>> + Â Âif (d->rom.base_addr && d->rom.size) {
>> + Â Â Â Â/* Re-set BAR reported by OS, otherwise ROM can't be read. */
>> + Â Â Â Âbar_data = host_pci_get_long(d, PCI_ROM_ADDRESS);
>> + Â Â Â Âif ((bar_data & PCI_ROM_ADDRESS_MASK) == 0) {
>> + Â Â Â Â Â Âbar_data |= d->rom.base_addr & PCI_ROM_ADDRESS_MASK;
>> + Â Â Â Â Â Âhost_pci_set_long(d, PCI_ROM_ADDRESS, bar_data);
>> + Â Â Â Â}
>> +
>> + Â Â Â Âs->bases[PCI_ROM_SLOT].e_physbase = d->rom.base_addr;
>> + Â Â Â Âs->bases[PCI_ROM_SLOT].access.maddr = d->rom.base_addr;
>> +
>> + Â Â Â Âmemory_region_init_rom_device(&s->rom, NULL, NULL, &s->dev.qdev,
>> + Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â"xen-pci-pt-rom", d->rom.size);
>> + Â Â Â Âpci_register_bar(&s->dev, PCI_ROM_SLOT,
>> PCI_BASE_ADDRESS_MEM_PREFETCH,
>> + Â Â Â Â Â Â Â Â Â Â Â Â &s->rom);
>> +
>> + Â Â Â ÂPT_LOG("Expansion ROM registered (size=0x%08"PRIx64
>> + Â Â Â Â Â Â Â " base_addr=0x%08"PRIx64")\n",
>> + Â Â Â Â Â Â Â d->rom.size, d->rom.base_addr);
>> + Â Â}
>> +
>> + Â Âreturn 0;
>> +}
>> +
>> +static void pt_unregister_regions(XenPCIPassthroughState *s)
>> +{
>> + Â Âint i, type, rc;
>> + Â Âuint32_t e_size;
>> + Â ÂPCIDevice *d = &s->dev;
>> +
>> + Â Âfor (i = 0; i < PCI_NUM_REGIONS; i++) {
>> + Â Â Â Âe_size = s->bases[i].e_size;
>> + Â Â Â Âif ((e_size == 0) || (s->bases[i].e_physbase == -1)) {
>> + Â Â Â Â Â Âcontinue;
>> + Â Â Â Â}
>> +
>> + Â Â Â Âtype = d->io_regions[i].type;
>> +
>> + Â Â Â Âif (type == PCI_BASE_ADDRESS_SPACE_MEMORY
>> + Â Â Â Â Â Â|| type == PCI_BASE_ADDRESS_MEM_PREFETCH) {
>> + Â Â Â Â Â Ârc = xc_domain_memory_mapping(xen_xc, xen_domid,
>> + Â Â Â Â Â Â Â Â Â Âs->bases[i].e_physbase >> XC_PAGE_SHIFT,
>> + Â Â Â Â Â Â Â Â Â Âs->bases[i].access.maddr >> XC_PAGE_SHIFT,
>> + Â Â Â Â Â Â Â Â Â Â(e_size+XC_PAGE_SIZE-1) >> XC_PAGE_SHIFT,
>> + Â Â Â Â Â Â Â Â Â ÂDPCI_REMOVE_MAPPING);
>> + Â Â Â Â Â Âif (rc != 0) {
>> + Â Â Â Â Â Â Â ÂPT_LOG("Error: remove old mem mapping failed!\n");
>> + Â Â Â Â Â Â Â Âcontinue;
>> + Â Â Â Â Â Â}
>> +
>> + Â Â Â Â} else if (type == PCI_BASE_ADDRESS_SPACE_IO) {
>> + Â Â Â Â Â Ârc = xc_domain_ioport_mapping(xen_xc, xen_domid,
>> + Â Â Â Â Â Â Â Â Â Â Â Âs->bases[i].e_physbase,
>> + Â Â Â Â Â Â Â Â Â Â Â Âs->bases[i].access.pio_base,
>> + Â Â Â Â Â Â Â Â Â Â Â Âe_size,
>> + Â Â Â Â Â Â Â Â Â Â Â ÂDPCI_REMOVE_MAPPING);
>> + Â Â Â Â Â Âif (rc != 0) {
>> + Â Â Â Â Â Â Â ÂPT_LOG("Error: remove old io mapping failed!\n");
>> + Â Â Â Â Â Â Â Âcontinue;
>> + Â Â Â Â Â Â}
>> + Â Â Â Â}
>> + Â Â}
>> +}
>> +
>> +static int pt_initfn(PCIDevice *pcidev)
>> +{
>> + Â ÂXenPCIPassthroughState *s = DO_UPCAST(XenPCIPassthroughState, dev,
>> pcidev);
>> + Â Âint dom, bus;
>> + Â Âunsigned slot, func;
>> + Â Âint rc = 0;
>> + Â Âuint32_t machine_irq;
>> + Â Âint pirq = -1;
>> +
>> + Â Âif (pci_parse_devaddr(s->hostaddr, &dom, &bus, &slot, &func) < 0) {
>> + Â Â Â Âfprintf(stderr, "error parse bdf: %s\n", s->hostaddr);
>> + Â Â Â Âreturn -1;
>> + Â Â}
>> +
>> + Â Â/* register real device */
>> + Â ÂPT_LOG("Assigning real physical device %02x:%02x.%x to devfn %i ...\n",
>> + Â Â Â Â Â bus, slot, func, s->dev.devfn);
>> +
>> + Â Âs->real_device = host_pci_device_get(bus, slot, func);
>> + Â Âif (!s->real_device) {
>> + Â Â Â Âreturn -1;
>> + Â Â}
>> +
>> + Â Âs->is_virtfn = s->real_device->is_virtfn;
>> + Â Âif (s->is_virtfn) {
>> + Â Â Â ÂPT_LOG("%04x:%02x:%02x.%x is a SR-IOV Virtual Function\n",
>> + Â Â Â Â Â Â Â s->real_device->domain, bus, slot, func);
>> + Â Â}
>> +
>> + Â Â/* Initialize virtualized PCI configuration (Extended 256 Bytes) */
>> + Â Âif (host_pci_get_block(s->real_device, 0, pcidev->config,
>> + Â Â Â Â Â Â Â Â Â Â Â Â Â PCI_CONFIG_SPACE_SIZE) == -1) {
>> + Â Â Â Âreturn -1;
>> + Â Â}
>> +
>> + Â Â/* Handle real device's MMIO/PIO BARs */
>> + Â Âpt_register_regions(s);
>> +
>> + Â Â/* reinitialize each config register to be emulated */
>> + Â Âpt_config_init(s);
>
> this function is implemented in the next patch, so you might as well add
> this call there
Ok, I will move this.
>> + Â Â/* Bind interrupt */
>> + Â Âif (!s->dev.config[PCI_INTERRUPT_PIN]) {
>> + Â Â Â ÂPT_LOG("no pin interrupt\n");
>> + Â Â Â Âgoto out;
>> + Â Â}
>> +
>> + Â Âmachine_irq = host_pci_get_byte(s->real_device, PCI_INTERRUPT_LINE);
>> + Â Ârc = xc_physdev_map_pirq(xen_xc, xen_domid, machine_irq, &pirq);
>> +
>> + Â Âif (rc) {
>> + Â Â Â ÂPT_LOG("Error: Mapping irq failed, rc = %d\n", rc);
>> +
>> + Â Â Â Â/* Disable PCI intx assertion (turn on bit10 of devctl) */
>> + Â Â Â Âhost_pci_set_word(s->real_device,
>> + Â Â Â Â Â Â Â Â Â Â Â Â ÂPCI_COMMAND,
>> + Â Â Â Â Â Â Â Â Â Â Â Â Âpci_get_word(s->dev.config + PCI_COMMAND)
>> + Â Â Â Â Â Â Â Â Â Â Â Â Â| PCI_COMMAND_INTX_DISABLE);
>> + Â Â Â Âmachine_irq = 0;
>> + Â Â Â Âs->machine_irq = 0;
>> + Â Â} else {
>> + Â Â Â Âmachine_irq = pirq;
>> + Â Â Â Âs->machine_irq = pirq;
>> + Â Â Â Âmapped_machine_irq[machine_irq]++;
>> + Â Â}
>> +
>> + Â Â/* bind machine_irq to device */
>> + Â Âif (rc < 0 && machine_irq != 0) {
>> + Â Â Â Âuint8_t e_device = PCI_SLOT(s->dev.devfn);
>> + Â Â Â Âuint8_t e_intx = pci_intx(s);
>> +
>> + Â Â Â Ârc = xc_domain_bind_pt_pci_irq(xen_xc, xen_domid, machine_irq, 0,
>> + Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â e_device, e_intx);
>> + Â Â Â Âif (rc < 0) {
>> + Â Â Â Â Â ÂPT_LOG("Error: Binding of interrupt failed! rc=%d\n", rc);
>> +
>> + Â Â Â Â Â Â/* Disable PCI intx assertion (turn on bit10 of devctl) */
>> + Â Â Â Â Â Âhost_pci_set_word(s->real_device, PCI_COMMAND,
>> + Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â*(uint16_t *)(&s->dev.config[PCI_COMMAND])
>> + Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â| PCI_COMMAND_INTX_DISABLE);
>> + Â Â Â Â Â Âmapped_machine_irq[machine_irq]--;
>> +
>> + Â Â Â Â Â Âif (mapped_machine_irq[machine_irq] == 0) {
>> + Â Â Â Â Â Â Â Âif (xc_physdev_unmap_pirq(xen_xc, xen_domid, machine_irq)) {
>> + Â Â Â Â Â Â Â Â Â ÂPT_LOG("Error: Unmapping of interrupt failed! rc=%d\n",
>> + Â Â Â Â Â Â Â Â Â Â Â Â Â rc);
>> + Â Â Â Â Â Â Â Â}
>> + Â Â Â Â Â Â}
>> + Â Â Â Â Â Âs->machine_irq = 0;
>> + Â Â Â Â}
>> + Â Â}
>> +
>> +out:
>> + Â ÂPT_LOG("Real physical device %02x:%02x.%x registered successfuly!\n"
>> + Â Â Â Â Â "IRQ type = %s\n", bus, slot, func, "INTx");
>> +
>> + Â Âreturn 0;
>> +}
>> +
>> +static int pt_unregister_device(PCIDevice *pcidev)
>> +{
>> + Â ÂXenPCIPassthroughState *s = DO_UPCAST(XenPCIPassthroughState, dev,
>> pcidev);
>> + Â Âuint8_t e_device, e_intx;
>> + Â Âuint32_t machine_irq;
>> + Â Âint rc;
>> +
>> + Â Â/* Unbind interrupt */
>> + Â Âe_device = PCI_SLOT(s->dev.devfn);
>> + Â Âe_intx = pci_intx(s);
>> + Â Âmachine_irq = s->machine_irq;
>> +
>> + Â Âif (machine_irq) {
>> + Â Â Â Ârc = xc_domain_unbind_pt_irq(xen_xc, xen_domid, machine_irq,
>> + Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â PT_IRQ_TYPE_PCI, 0, e_device, e_intx,
>> 0);
>> + Â Â Â Âif (rc < 0) {
>> + Â Â Â Â Â ÂPT_LOG("Error: Unbinding of interrupt failed! rc=%d\n", rc);
>> + Â Â Â Â}
>> + Â Â}
>> +
>> + Â Âif (machine_irq) {
>> + Â Â Â Âmapped_machine_irq[machine_irq]--;
>> +
>> + Â Â Â Âif (mapped_machine_irq[machine_irq] == 0) {
>> + Â Â Â Â Â Ârc = xc_physdev_unmap_pirq(xen_xc, xen_domid, machine_irq);
>> +
>> + Â Â Â Â Â Âif (rc < 0) {
>> + Â Â Â Â Â Â Â ÂPT_LOG("Error: Unmaping of interrupt failed! rc=%d\n", rc);
>> + Â Â Â Â Â Â}
>> + Â Â Â Â}
>> + Â Â}
>> +
>> + Â Â/* delete all emulated config registers */
>> + Â Âpt_config_delete(s);
>> +
>> + Â Â/* unregister real device's MMIO/PIO BARs */
>> + Â Âpt_unregister_regions(s);
>> +
>> + Â Âhost_pci_device_put(s->real_device);
>> +
>> + Â Âreturn 0;
>> +}
>> +
>> +static PCIDeviceInfo xen_pci_passthrough = {
>> + Â Â.init = pt_initfn,
>> + Â Â.exit = pt_unregister_device,
>> + Â Â.qdev.name = "xen-pci-passthrough",
>> + Â Â.qdev.desc = "Assign an host pci device with Xen",
>> + Â Â.qdev.size = sizeof(XenPCIPassthroughState),
>> + Â Â.config_read = pt_pci_read_config,
>> + Â Â.config_write = pt_pci_write_config,
>> + Â Â.is_express = 0,
>> + Â Â.qdev.props = (Property[]) {
>> + Â Â Â ÂDEFINE_PROP_STRING("hostaddr", XenPCIPassthroughState, hostaddr),
>> + Â Â Â ÂDEFINE_PROP_BIT("power-mgmt", XenPCIPassthroughState, power_mgmt,
>> + Â Â Â Â Â Â Â Â Â Â Â Â0, false),
>> + Â Â Â ÂDEFINE_PROP_END_OF_LIST(),
>> + Â Â}
>> +};
>> +
>> +static void xen_passthrough_register(void)
>> +{
>> + Â Âpci_qdev_register(&xen_pci_passthrough);
>> +}
>> +
>> +device_init(xen_passthrough_register);
>> diff --git a/hw/xen_pci_passthrough.h b/hw/xen_pci_passthrough.h
>> new file mode 100644
>> index 0000000..2d1979d
>> --- /dev/null
>> +++ b/hw/xen_pci_passthrough.h
>> @@ -0,0 +1,223 @@
>> +#ifndef QEMU_HW_XEN_PCI_PASSTHROUGH_H
>> +# Âdefine QEMU_HW_XEN_PCI_PASSTHROUGH_H
>> +
>> +#include "qemu-common.h"
>> +#include "xen_common.h"
>> +#include "pci.h"
>> +#include "host-pci-device.h"
>> +
>> +#define PT_LOGGING_ENABLED
>> +#define PT_DEBUG_PCI_CONFIG_ACCESS
>> +
>> +#ifdef PT_LOGGING_ENABLED
>> +# Âdefine PT_LOG(_f, _a...) Â fprintf(stderr, "%s: " _f, __func__, ##_a)
>> +#else
>> +# Âdefine PT_LOG(_f, _a...)
>> +#endif
>> +
>> +#ifdef PT_DEBUG_PCI_CONFIG_ACCESS
>> +# Âdefine PT_LOG_CONFIG(_f, _a...) PT_LOG(_f, ##_a)
>> +#else
>> +# Âdefine PT_LOG_CONFIG(_f, _a...)
>> +#endif
>> +
>> +
>> +typedef struct XenPTRegInfo XenPTRegInfo;
>> +typedef struct XenPTReg XenPTReg;
>> +
>> +typedef struct XenPCIPassthroughState XenPCIPassthroughState;
>> +
>> +/* function type for config reg */
>> +typedef uint32_t (*conf_reg_init)
>> + Â Â(XenPCIPassthroughState *, XenPTRegInfo *, uint32_t real_offset);
>> +typedef int (*conf_dword_write)
>> + Â Â(XenPCIPassthroughState *, XenPTReg *cfg_entry,
>> + Â Â uint32_t *val, uint32_t dev_value, uint32_t valid_mask);
>> +typedef int (*conf_word_write)
>> + Â Â(XenPCIPassthroughState *, XenPTReg *cfg_entry,
>> + Â Â uint16_t *val, uint16_t dev_value, uint16_t valid_mask);
>> +typedef int (*conf_byte_write)
>> + Â Â(XenPCIPassthroughState *, XenPTReg *cfg_entry,
>> + Â Â uint8_t *val, uint8_t dev_value, uint8_t valid_mask);
>> +typedef int (*conf_dword_read)
>> + Â Â(XenPCIPassthroughState *, XenPTReg *cfg_entry,
>> + Â Â uint32_t *val, uint32_t valid_mask);
>> +typedef int (*conf_word_read)
>> + Â Â(XenPCIPassthroughState *, XenPTReg *cfg_entry,
>> + Â Â uint16_t *val, uint16_t valid_mask);
>> +typedef int (*conf_byte_read)
>> + Â Â(XenPCIPassthroughState *, XenPTReg *cfg_entry,
>> + Â Â uint8_t *val, uint8_t valid_mask);
>> +typedef int (*conf_dword_restore)
>> + Â Â(XenPCIPassthroughState *, XenPTReg *cfg_entry, uint32_t real_offset,
>> + Â Â uint32_t dev_value, uint32_t *val);
>> +typedef int (*conf_word_restore)
>> + Â Â(XenPCIPassthroughState *, XenPTReg *cfg_entry, uint32_t real_offset,
>> + Â Â uint16_t dev_value, uint16_t *val);
>> +typedef int (*conf_byte_restore)
>> + Â Â(XenPCIPassthroughState *, XenPTReg *cfg_entry, uint32_t real_offset,
>> + Â Â uint8_t dev_value, uint8_t *val);
>> +
>> +/* power state transition */
>> +#define PT_FLAG_TRANSITING 0x0001
>> +
>> +
>> +typedef enum {
>> + Â ÂGRP_TYPE_HARDWIRED = 0, Â Â Â Â Â Â Â Â Â Â /* 0 Hardwired reg group */
>> + Â ÂGRP_TYPE_EMU, Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â /* emul reg group */
>> +} RegisterGroupType;
>> +
>> +typedef enum {
>> + Â ÂPT_BAR_FLAG_MEM = 0, Â Â Â Â Â Â Â Â Â Â Â Â/* Memory type BAR */
>> + Â ÂPT_BAR_FLAG_IO, Â Â Â Â Â Â Â Â Â Â Â Â Â Â /* I/O type BAR */
>> + Â ÂPT_BAR_FLAG_UPPER, Â Â Â Â Â Â Â Â Â Â Â Â Â/* upper 64bit BAR */
>> + Â ÂPT_BAR_FLAG_UNUSED, Â Â Â Â Â Â Â Â Â Â Â Â /* unused BAR */
>> +} PTBarFlag;
>> +
>> +
>> +typedef struct XenPTRegion {
>> + Â Â/* Virtual phys base & size */
>> + Â Âuint32_t e_physbase;
>> + Â Âuint32_t e_size;
>> + Â Â/* Index of region in qemu */
>> + Â Âuint32_t memory_index;
>> + Â Â/* BAR flag */
>> + Â ÂPTBarFlag bar_flag;
>> + Â Â/* Translation of the emulated address */
>> + Â Âunion {
>> + Â Â Â Âuint64_t maddr;
>> + Â Â Â Âuint64_t pio_base;
>> + Â Â Â Âuint64_t u;
>> + Â Â} access;
>> +} XenPTRegion;
>> +
>> +/* XenPTRegInfo declaration
>> + * - only for emulated register (either a part or whole bit).
>> + * - for passthrough register that need special behavior (like interacting
>> with
>> + * Â other component), set emu_mask to all 0 and specify r/w func properly.
>> + * - do NOT use ALL F for init_val, otherwise the tbl will not be
>> registered.
>> + */
>> +
>> +/* emulated register infomation */
>> +struct XenPTRegInfo {
>> + Â Âuint32_t offset;
>> + Â Âuint32_t size;
>> + Â Âuint32_t init_val;
>> + Â Â/* reg read only field mask (ON:RO/ROS, OFF:other) */
>> + Â Âuint32_t ro_mask;
>> + Â Â/* reg emulate field mask (ON:emu, OFF:passthrough) */
>> + Â Âuint32_t emu_mask;
>> + Â Â/* no write back allowed */
>> + Â Âuint32_t no_wb;
>> + Â Âconf_reg_init init;
>> + Â Â/* read/write/restore function pointer
>> + Â Â * for double_word/word/byte size */
>> + Â Âunion {
>> + Â Â Â Âstruct {
>> + Â Â Â Â Â Âconf_dword_write write;
>> + Â Â Â Â Â Âconf_dword_read read;
>> + Â Â Â Â Â Âconf_dword_restore restore;
>> + Â Â Â Â} dw;
>> + Â Â Â Âstruct {
>> + Â Â Â Â Â Âconf_word_write write;
>> + Â Â Â Â Â Âconf_word_read read;
>> + Â Â Â Â Â Âconf_word_restore restore;
>> + Â Â Â Â} w;
>> + Â Â Â Âstruct {
>> + Â Â Â Â Â Âconf_byte_write write;
>> + Â Â Â Â Â Âconf_byte_read read;
>> + Â Â Â Â Â Âconf_byte_restore restore;
>> + Â Â Â Â} b;
>> + Â Â} u;
>> +};
>> +
>> +/* emulated register management */
>> +struct XenPTReg {
>> + Â ÂQLIST_ENTRY(XenPTReg) entries;
>> + Â ÂXenPTRegInfo *reg;
>> + Â Âuint32_t data;
>> +};
>> +
>> +typedef struct XenPTRegGroupInfo XenPTRegGroupInfo;
>> +
>> +/* emul reg group size initialize method */
>> +typedef uint8_t (*pt_reg_size_init_fn)
>> + Â Â(XenPCIPassthroughState *, const XenPTRegGroupInfo *,
>> + Â Â uint32_t base_offset);
>> +
>> +/* emulated register group infomation */
>> +struct XenPTRegGroupInfo {
>> + Â Âuint8_t grp_id;
>> + Â ÂRegisterGroupType grp_type;
>> + Â Âuint8_t grp_size;
>> + Â Âpt_reg_size_init_fn size_init;
>> + Â ÂXenPTRegInfo *emu_reg_tbl;
>> +};
>> +
>> +/* emul register group management table */
>> +typedef struct XenPTRegGroup {
>> + Â ÂQLIST_ENTRY(XenPTRegGroup) entries;
>> + Â Âconst XenPTRegGroupInfo *reg_grp;
>> + Â Âuint32_t base_offset;
>> + Â Âuint8_t size;
>> + Â ÂQLIST_HEAD(, XenPTReg) reg_tbl_list;
>> +} XenPTRegGroup;
>> +
>> +
>> +typedef struct XenPTPM {
>> + Â ÂQEMUTimer *pm_timer; Â/* QEMUTimer struct */
>> + Â Âint no_soft_reset; Â Â/* No Soft Reset flags */
>> + Â Âuint16_t flags; Â Â Â /* power state transition flags */
>> + Â Âuint16_t pmc_field; Â /* Power Management Capabilities field */
>> + Â Âint pm_delay; Â Â Â Â /* power state transition delay */
>> + Â Âuint16_t cur_state; Â /* current power state */
>> + Â Âuint16_t req_state; Â /* requested power state */
>> + Â Âuint32_t pm_base; Â Â /* Power Management Capability reg base offset */
>> + Â Âuint32_t aer_base; Â Â/* AER Capability reg base offset */
>> +} XenPTPM;
>> +
>> +struct XenPCIPassthroughState {
>> + Â ÂPCIDevice dev;
>> +
>> + Â Âchar *hostaddr;
>> + Â Âbool is_virtfn;
>> + Â ÂHostPCIDevice *real_device;
>> + Â ÂXenPTRegion bases[PCI_NUM_REGIONS]; /* Access regions */
>> + Â ÂQLIST_HEAD(, XenPTRegGroup) reg_grp_tbl;
>> +
>> + Â Âuint32_t machine_irq;
>> +
>> + Â Âuint32_t power_mgmt;
>> + Â ÂXenPTPM *pm_state;
>> +
>> + Â ÂMemoryRegion bar[PCI_NUM_REGIONS - 1];
>> + Â ÂMemoryRegion rom;
>> +};
>> +
>> +void pt_config_init(XenPCIPassthroughState *s);
>> +void pt_config_delete(XenPCIPassthroughState *s);
>> +void pt_bar_mapping(XenPCIPassthroughState *s, int io_enable, int
>> mem_enable);
>> +void pt_bar_mapping_one(XenPCIPassthroughState *s, int bar,
>> + Â Â Â Â Â Â Â Â Â Â Â Âint io_enable, int mem_enable);
>> +XenPTRegGroup *pt_find_reg_grp(XenPCIPassthroughState *s, uint32_t address);
>> +XenPTReg *pt_find_reg(XenPTRegGroup *reg_grp, uint32_t address);
>> +int pt_bar_offset_to_index(uint32_t offset);
>> +
>> +static inline pcibus_t pt_get_emul_size(PTBarFlag flag, pcibus_t r_size)
>> +{
>> + Â Â/* align resource size (memory type only) */
>> + Â Âif (flag == PT_BAR_FLAG_MEM) {
>> + Â Â Â Âreturn (r_size + XC_PAGE_SIZE - 1) & XC_PAGE_MASK;
>> + Â Â} else {
>> + Â Â Â Âreturn r_size;
>> + Â Â}
>> +}
>> +
>> +/* INTx */
>> +static inline uint8_t pci_read_intx(XenPCIPassthroughState *s)
>> +{
>> + Â Âreturn host_pci_get_byte(s->real_device, PCI_INTERRUPT_PIN);
>> +}
>> +uint8_t pci_intx(XenPCIPassthroughState *ptdev);
>> +
>> +#endif /* !QEMU_HW_XEN_PCI_PASSTHROUGH_H */
>> diff --git a/hw/xen_pci_passthrough_helpers.c
>> b/hw/xen_pci_passthrough_helpers.c
>> new file mode 100644
>> index 0000000..192e918
>> --- /dev/null
>> +++ b/hw/xen_pci_passthrough_helpers.c
>> @@ -0,0 +1,46 @@
>> +#include "xen_pci_passthrough.h"
>> +
>> +/* The PCI Local Bus Specification, Rev. 3.0, {
>> + * Section 6.2.4 Miscellaneous Registers, pp 223
>> + * outlines 5 valid values for the intertupt pin (intx).
>> + * Â0: For devices (or device functions) that don't use an interrupt in
>> + * Â1: INTA#
>> + * Â2: INTB#
>> + * Â3: INTC#
>> + * Â4: INTD#
>> + *
>> + * Xen uses the following 4 values for intx
>> + * Â0: INTA#
>> + * Â1: INTB#
>> + * Â2: INTC#
>> + * Â3: INTD#
>> + *
>> + * Observing that these list of values are not the same, pci_read_intx()
>> + * uses the following mapping from hw to xen values.
>> + * This seems to reflect the current usage within Xen.
>> + *
>> + * PCI hardware  Â| Xen | Notes
>> + *
>> ----------------+-----+----------------------------------------------------
>> + * 0 Â Â Â Â Â Â Â | 0 Â | No interrupt
>> + * 1 Â Â Â Â Â Â Â | 0 Â | INTA#
>> + * 2 Â Â Â Â Â Â Â | 1 Â | INTB#
>> + * 3 Â Â Â Â Â Â Â | 2 Â | INTC#
>> + * 4 Â Â Â Â Â Â Â | 3 Â | INTD#
>> + * any other value | 0 Â | This should never happen, log error message
>> +}
>> + */
>> +uint8_t pci_intx(XenPCIPassthroughState *ptdev)
>> +{
>> + Â Âuint8_t r_val = pci_read_intx(ptdev);
>> +
>> + Â ÂPT_LOG("intx=%i\n", r_val);
>> + Â Âif (r_val < 1 || r_val > 4) {
>> + Â Â Â ÂPT_LOG("Interrupt pin read from hardware is out of range: "
>> + Â Â Â Â Â Â Â "value=%i, acceptable range is 1 - 4\n", r_val);
>> + Â Â Â Âr_val = 0;
>> + Â Â} else {
>> + Â Â Â Âr_val -= 1;
>> + Â Â}
>> +
>> + Â Âreturn r_val;
>> +}
>
> if xen_pci_passthrough_helpers.c is only going to contain this function
> you might as well declared it static inline and move it to
> xen_pci_passthrough.h
Ok, I will.
--
Anthony PERARD
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