[Xen-devel] [PATCH 6 of 6] amd iommu: Introduce iommu_has_cap() function

[Wei Wang <wei.wang2@xxxxxxx>]

# HG changeset patch
# User Wei Wang <wei.wang2@xxxxxxx>
# Date 1320852003 -3600
# Node ID fc109be12bf682299b47ea8ebb549afc6ac52952
# Parent  c75cf540a1fe57a439f9cb0503bf69f120066b92
amd iommu: Introduce iommu_has_cap() function.
Signed-off-by: Wei Wang <wei.wang2@xxxxxxx>

diff -r c75cf540a1fe -r fc109be12bf6 xen/drivers/passthrough/amd/iommu_init.c
--- a/xen/drivers/passthrough/amd/iommu_init.c  Wed Nov 09 16:20:03 2011 +0100
+++ b/xen/drivers/passthrough/amd/iommu_init.c  Wed Nov 09 16:20:03 2011 +0100
@@ -79,9 +79,12 @@ static void set_iommu_ht_flags(struct am
     entry = readl(iommu->mmio_base + IOMMU_CONTROL_MMIO_OFFSET);
 
     /* Setup HT flags */
-    iommu_has_ht_flag(iommu, AMD_IOMMU_ACPI_HT_TUN_ENB_SHIFT) ?
+    if ( iommu_has_cap(iommu, PCI_CAP_HT_TUNNEL_SHIFT) )
+    {
+        iommu_has_ht_flag(iommu, AMD_IOMMU_ACPI_HT_TUN_ENB_SHIFT) ?
         iommu_set_bit(&entry, IOMMU_CONTROL_HT_TUNNEL_TRANSLATION_SHIFT):
         iommu_clear_bit(&entry, IOMMU_CONTROL_HT_TUNNEL_TRANSLATION_SHIFT);
+    }
 
     iommu_has_ht_flag(iommu, AMD_IOMMU_ACPI_RES_PASS_PW_SHIFT) ?
         iommu_set_bit(&entry, IOMMU_CONTROL_RESP_PASS_POSTED_WRITE_SHIFT):
diff -r c75cf540a1fe -r fc109be12bf6 xen/drivers/passthrough/amd/iommu_map.c
--- a/xen/drivers/passthrough/amd/iommu_map.c   Wed Nov 09 16:20:03 2011 +0100
+++ b/xen/drivers/passthrough/amd/iommu_map.c   Wed Nov 09 16:20:03 2011 +0100
@@ -996,7 +996,7 @@ void amd_iommu_flush_iotlb(struct pci_de
         return;
     }
 
-    if ( !iommu->iotlb_support )
+    if ( !iommu_has_cap(iommu, PCI_CAP_IOTLB_SHIFT) )
         return;
 
     req_id = get_dma_requestor_id(iommu->seg, bdf);
diff -r c75cf540a1fe -r fc109be12bf6 xen/drivers/passthrough/amd/pci_amd_iommu.c
--- a/xen/drivers/passthrough/amd/pci_amd_iommu.c       Wed Nov 09 16:20:03 
2011 +0100
+++ b/xen/drivers/passthrough/amd/pci_amd_iommu.c       Wed Nov 09 16:20:03 
2011 +0100
@@ -115,7 +115,7 @@ static void amd_iommu_setup_domain_devic
             hd->paging_mode, valid);
 
         if ( pci_ats_device(iommu->seg, bus, devfn) &&
-             iommu->iotlb_support )
+             iommu_has_cap(iommu, PCI_CAP_IOTLB_SHIFT) )
             iommu_dte_set_iotlb((u32 *)dte, dte_i);
 
         invalidate_dev_table_entry(iommu, req_id);
@@ -307,7 +307,7 @@ void amd_iommu_disable_domain_device(str
         disable_translation((u32 *)dte);
 
         if ( pci_ats_device(iommu->seg, bus, devfn) &&
-             iommu->iotlb_support )
+             iommu_has_cap(iommu, PCI_CAP_IOTLB_SHIFT) )
             iommu_dte_set_iotlb((u32 *)dte, 0);
 
         invalidate_dev_table_entry(iommu, req_id);
diff -r c75cf540a1fe -r fc109be12bf6 xen/include/asm-x86/amd-iommu.h
--- a/xen/include/asm-x86/amd-iommu.h   Wed Nov 09 16:20:03 2011 +0100
+++ b/xen/include/asm-x86/amd-iommu.h   Wed Nov 09 16:20:03 2011 +0100
@@ -53,10 +53,6 @@ struct amd_iommu {
     u16 cap_offset;
     iommu_cap_t cap;
 
-    u8 pte_not_present_cached;
-    u8 ht_tunnel_support;
-    u8 iotlb_support;
-
     u8 ht_flags;
 
     void *mmio_base;
diff -r c75cf540a1fe -r fc109be12bf6 
xen/include/asm-x86/hvm/svm/amd-iommu-proto.h
--- a/xen/include/asm-x86/hvm/svm/amd-iommu-proto.h     Wed Nov 09 16:20:03 
2011 +0100
+++ b/xen/include/asm-x86/hvm/svm/amd-iommu-proto.h     Wed Nov 09 16:20:03 
2011 +0100
@@ -181,4 +181,10 @@ static inline uint32_t iommu_get_bit(uin
     return get_field_from_reg_u32(reg, 1U << bit, bit);
 }
 
+static inline int iommu_has_cap(struct amd_iommu *iommu, uint32_t bit)
+{
+    u32 mask = (1U << bit) & 0xffffffff;
+    return iommu->cap.header & mask;
+}
+
 #endif /* _ASM_X86_64_AMD_IOMMU_PROTO_H */


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