On May 23, 2011, at 4:26 AM, Jan Beulich wrote:
The PS/2 port has a one character buffer. It will only ever send one
interrupt until it has been serviced. When __do_IRQ_guest calls
send_guest_pirq and sees that it is already pending, what part of the between
the bottom of __do_IRQ_guest and _irq_guest_eoi results in the pending
interrupt being issued to the guest? I haven't found that and it looks like
Xen is merging the ACKTYPE_NONE edge interrupt resulting in the deice never
being serviced when it's buffer is full and never interrupting again.
It would be a bug of the 8042 if it sent a second interrupt when the first one wasn't serviced (status and data port read) yet. It's the nature of edge triggered interrupts that secondary instances are lost when the primary instance doesn't get handled (in time). Jan
My assumption is that at the point that the i8042 driver reads the data register a new interrupt happens. There is gap in time between when the data register is read and when the event channel pending state is cleared. Since the hypervisor ACKed the previous real interrupt before delivering it to the guest, there is nothing to stop the i8042 device from interrupting immediately after the data register is read. If it interrupt before the event channel pending state is cleared, then it will not be delivered to the guest and the EOI mechanism will be set up, but I haven't found anything in that that will set up a delayed delivery of the second interrupt.
In this situation the i8042 device has every reason to believe the second interrupt will be delivered. The previous interrupt was received and handled. Nothing is masked.
Am I missing something?
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