[Date Prev][Date Next][Thread Prev][Thread Next][Date Index][Thread Index] RE: [Xen-devel] [PATCH 4] MCA physical address check when calculate domain
Jan Beulich wrote: >>>> On 10.05.11 at 08:38, "Liu, Jinsong" <jinsong.liu@xxxxxxxxx> wrote: >> As for physical addr, the addr in MCi_ADDR reg may be linear add/ >> physical add/ setment offset. according to Intel SDM, the addr in >> MCi_ADDR reg is physical addr only when: 1). MISCV bit of MCi_STATUS >> set; 2). ADDRV bit of MCi_STATUS set; >> 3). address mode of MCi_MISC (bit 6~8) = 010; > > I realize this is what's being documented currently. Going back to the > newest hard copy manual I still have (PentiumPro, which luckily is the > first one where the banked implementation is described), there's no > MCi_MISC (it's documented, but said to not be implemented on these > old CPUs), and the description for the address reads "The address > returned is either 32-bit virtual, 32-bit linear, or 36-bit > physical". Now I certainly don't care much about PPro anymore, but I > wonder when MCi_MISC was first implemented in the way your patch is > using it. > Seems needn't care about when MCi_MISC first implemented. MCi_STATUS_MISCV check can make sure accessing MCi_MISC safely. If really want to know MCi_MISC implemented at which processor, we can use cpuid DF_DM as clue. Different MCi_MISC implemented at different DF_DM processors (refer Intel SDM, Appendix B). Currently there are 22 MCi_MISC (refer Table B-2), generally MC0~4_MISC implement for all P6 processors; MC5_MISC after 06_0F; MC6_MISC after 06_1D; ... MC21_MISC after 06_2E; However, if want to check exactually how many MCi_MISC reg a processor has, it has to check 'count' field of IA32_MCG_CAP. Take SNB processor (refer Table B-10) as example: It only support MC0~3_MISC openly (this does mean it has no other MCi_MISC, but means we can use MC0~3_MISC SAFELY). > Further, the current manual also makes a distinction between > "Physical Address" and "Memory Address", and additionally has > a "Generic" type - all without further explanation. > > Jan Memory address is from the view of memory controller, say, channel number, as far as I understand. I don't know what 'Generic' means either. Thanks, Jinsong _______________________________________________ Xen-devel mailing list Xen-devel@xxxxxxxxxxxxxxxxxxx http://lists.xensource.com/xen-devel
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