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[Xen-devel] [PATCH][RFC] FPU LWP 0/5: patch description

To: "'xen-devel@xxxxxxxxxxxxxxxxxxx'" <xen-devel@xxxxxxxxxxxxxxxxxxx>
From: Wei Huang <wei.huang2@xxxxxxx>
Date: Thu, 14 Apr 2011 15:37:27 -0500
Delivery-date: Thu, 14 Apr 2011 13:41:54 -0700
List-id: Xen developer discussion <xen-devel.lists.xensource.com>

The following patches support AMD lightweight profiling.

Because LWP isn't tracked by CR0.TS bit, we clean up the FPU code tohandle lazy and unlazy FPU states differently. Lazy FPU state (such asSSE, YMM) is handled when #NM is triggered. Unlazy state, such as LWP,is saved and restored on each vcpu context switch. To simplify the code,we also add a mask option to xsave/xrstor function.


Thanks,
-Wei



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