[Date Prev][Date Next][Thread Prev][Thread Next][Date Index][Thread Index] [Xen-devel] [PATCH] x86: unmask CPUID levels on Intel CPUs
x86: unmask CPUID levels on Intel CPUs If the CPUID limit bit in MSR_IA32_MISC_ENABLE is set, clear it to make all CPUID information available. This is required for some features to work, such as MWAIT in cpuidle, get cpu topology, XSAVE, etc. Signed-off-by: Wei Gang <gang.wei@xxxxxxxxx> diff -r 0efb8a38bbf6 xen/arch/x86/cpu/intel.c --- a/xen/arch/x86/cpu/intel.c Fri Jul 23 11:00:37 2010 +0800 +++ b/xen/arch/x86/cpu/intel.c Fri Jul 23 16:27:42 2010 +0800 @@ -90,6 +90,20 @@ void __devinit early_intel_workaround(st /* Netburst reports 64 bytes clflush size, but does IO in 128 bytes */ if (c->x86 == 15 && c->x86_cache_alignment == 64) c->x86_cache_alignment = 128; + + /* Unmask CPUID levels if masked: */ + if (c->x86 > 6 || (c->x86 == 6 && c->x86_model >= 0xd)) { + u64 misc_enable; + + rdmsrl(MSR_IA32_MISC_ENABLE, misc_enable); + + if (misc_enable & MSR_IA32_MISC_ENABLE_LIMIT_CPUID) { + misc_enable &= ~MSR_IA32_MISC_ENABLE_LIMIT_CPUID; + wrmsrl(MSR_IA32_MISC_ENABLE, misc_enable); + c->cpuid_level = cpuid_eax(0); + printk("revised cpuid_level = %d\n", c->cpuid_level); + } + } } /* diff -r 0efb8a38bbf6 xen/include/asm-x86/msr-index.h --- a/xen/include/asm-x86/msr-index.h Fri Jul 23 11:00:37 2010 +0800 +++ b/xen/include/asm-x86/msr-index.h Fri Jul 23 15:58:40 2010 +0800 @@ -324,6 +324,7 @@ #define MSR_IA32_MISC_ENABLE_BTS_UNAVAIL (1<<11) #define MSR_IA32_MISC_ENABLE_PEBS_UNAVAIL (1<<12) #define MSR_IA32_MISC_ENABLE_MONITOR_ENABLE (1<<18) +#define MSR_IA32_MISC_ENABLE_LIMIT_CPUID (1<<22) #define MSR_IA32_MISC_ENABLE_XTPR_DISABLE (1<<23) /* Intel Model 6 */ Attachment:
wr_limit_cpuid.patch _______________________________________________ Xen-devel mailing list Xen-devel@xxxxxxxxxxxxxxxxxxx http://lists.xensource.com/xen-devel
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