[Xen-devel] PCI pass-through / MSI question: Is 30(hex) the lower limit for pirq?

[Dante Cinco <dantecinco@xxxxxxxxx>]

I'm trying to bring up a Windows domU with PCI pass-through and it looks like Xen is running out of pirqs (see log below). I'm using Xen 4.0.0 and dom0 2.6.32.12 pv-ops and pci-stub to hide the PCIe device.

It looks like the first available pirq is 4e(hex) and the last available is 30(hex) and after that, Xen returns an msix error. What's the consequence of running out of pirqs?

/var/log/xen/qemu-dm-win.log:

pt_msix_update_one: Update msix entry 0 with pirq 4e gvec b0
pt_msix_update_one: Update msix entry 1 with pirq 4d gvec a0
pt_msix_update_one: Update msix entry 2 with pirq 4c gvec 90
pt_msix_update_one: Update msix entry 3 with pirq 4b gvec 80
pt_msix_update_one: Update msix entry 4 with pirq 4a gvec 70
pt_msix_update_one: Update msix entry 5 with pirq 49 gvec 60
pt_msix_update_one: Update msix entry 6 with pirq 48 gvec 82
pt_msix_update_one: Update msix entry 7 with pirq 47 gvec 72
pt_msix_update_one: Update msix entry 8 with pirq 46 gvec 62
pt_msix_update_one: Update msix entry 9 with pirq 45 gvec 52
pt_msix_update_one: Update msix entry a with pirq 44 gvec b3
pt_msix_update_one: Update msix entry b with pirq 43 gvec a3
pt_msix_update_one: Update msix entry c with pirq 42 gvec 93
pt_msix_update_one: Update msix entry d with pirq 41 gvec 83
pt_msix_update_one: Update msix entry e with pirq 40 gvec 73
pt_msix_update_one: Update msix entry f with pirq 3f gvec 63
pt_msix_update_one: Update msix entry 10 with pirq 3e gvec 53
pt_msix_update_one: Update msix entry 11 with pirq 3d gvec b4
pt_msix_update_one: Update msix entry 12 with pirq 3c gvec a4
pt_msix_update_one: Update msix entry 13 with pirq 3b gvec 94
pt_msix_update_one: Update msix entry 14 with pirq 3a gvec 84
pt_msix_update_one: Update msix entry 15 with pirq 39 gvec 74
pt_msix_update_one: Update msix entry 16 with pirq 38 gvec 64
pt_msix_update_one: Update msix entry 17 with pirq 37 gvec 54
pt_msix_update_one: Update msix entry 18 with pirq 36 gvec b5
pt_msix_update_one: Update msix entry 19 with pirq 35 gvec a5
pt_msix_update_one: Update msix entry 1a with pirq 34 gvec 95
pt_msix_update_one: Update msix entry 1b with pirq 33 gvec 85
pt_msix_update_one: Update msix entry 1c with pirq 32 gvec 75
pt_msix_update_one: Update msix entry 1d with pirq 31 gvec 65
pt_msix_update_one: Update msix entry 1e with pirq 30 gvec 55
pt_msix_update_one: Error: Mapping msix entry 1f

Dante
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