Re: [Xen-devel] Re: how to enable shadow page table? Do Ihavetorun HVM guest systems for shadow paging mode?

[Tim Deegan <Tim.Deegan@xxxxxxxxxx>]

At 16:40 +0000 on 19 Mar (1237480807), Long Wang wrote:
> So most of shadow PTE dirty bits are still set by the MMU when the MMU finds
> there is a write to a page and the PTE dirty bit is cleared?

The MMU will indeed do this if it finds this is the case.  However as I
said in almost all shadow PTEs we keep the Dirty bit set all the time so
the MMU has nothing to do.

> Is this
> behavior always performed, or shall I turn on a switch for the MMU to set
> the dirty bit?

Always-on.  The MMU's behaviour is described in the Intel SDMs vol 3
sections 3.6 to 3.12, or the AMD APMs vol 2 chapter 5.

And, again, this has nothing to do with the dirty-page bitmap maintained
by log-dirty mode.

Cheers,

Tim.

> Thanks.
> 
> long
> 
> -----Original Message-----
> From: Tim Deegan [mailto:Tim.Deegan@xxxxxxxxxx] 
> Sent: Thursday, March 19, 2009 11:16 AM
> To: Long Wang
> Cc: 'Jeremy Fitzhardinge'; 'Xen-devel'
> Subject: Re: [Xen-devel] Re: how to enable shadow page table? Do Ihavetorun
> HVM guest systems for shadow paging mode?
> 
> Hi,
> 
> At 15:55 +0000 on 19 Mar (1237478115), Long Wang wrote:
> > I am a little confused. You wrote: 
> > 1) "The dirty bit of a *shadow* PTE is usually set by _sh_propagate (since
> > we don't care about it) except for some optimizations to do with HVM video
> > RAM mappings, where it's set by the MMU." 
> > 
> > 2) "Only for the *shadow* PTE, since that's the only one the MMU ever
> > Sees". 
> > 
> > Do you mean that most of *shadow* PTE dirty bits (in PV) are set by
> > _sh_propagate() (through a read-only-bit-triggered interception)?
> 
> No, I mean that when _sh_propagate() makes a shadow PTE that has the R/W
> bit set, it usually sets the Dirty bit as well (to save the MMU the
> extra write cycle later).
> 
> Cheers,
> 
> Tim.
> 
> -- 
> Tim Deegan <Tim.Deegan@xxxxxxxxxx>
> Principal Software Engineer, Citrix Systems (R&D) Ltd.
> [Company #02300071, SL9 0DZ, UK.]
> 

-- 
Tim Deegan <Tim.Deegan@xxxxxxxxxx>
Principal Software Engineer, Citrix Systems (R&D) Ltd.
[Company #02300071, SL9 0DZ, UK.]

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