Re: [Xen-devel] [PATCH 10/24] xen: mask XSAVE from cpuid

["Jan Beulich" <jbeulich@xxxxxxxxxx>]

>>> Andi Kleen <andi@xxxxxxxxxxxxxx> 17.03.09 00:59 >>>
>"Jan Beulich" <jbeulich@xxxxxxxxxx> writes:
>
>>>>> Arjan van de Ven <arjan@xxxxxxxxxxxxx> 16.03.09 01:09 >>>
>>>Well.. pretty much all new instructions need Xen modifications due to
>>>the need to be emulate to deal with traps/vmexits/etc right? 
>>>So I don't quite see many cpuid bits that would NOT involve some Xen
>>>modification or another ;)
>>
>> No, new (user-mode accessible) instructions represent precisely the kind
>> of extension that do not require hypervisor (or OS) awareness (see SSE2
>> etc, AES, FMA). New registers otoh are examples of where awareness is
>> needed (SSE, AVX), as would be new privileged instructions.
>
>Whey would another hypothetical FP register extension need Xen support
>once it gets proper XSAVE support? I can't think of a reason why
>(assuming XSAVE support) it would need to know of a new kind of
>FP register or similar. They very likely won't appear in any 
>instructions that need mmio. Or are you worried about the real
>mode emulator?

No, properly coded xsave support will (hopefully) make user-visible context
extensions transparent to hypervisor and OS. But I was giving a general
example here, and the change from xmm to ymm registers is one that does
need hypervisor (and OS) changes.

Jan


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