[Xen-devel] [patch 0/3]Enable CMCI (Corrected Machine Check Error Interrupt) for Intel CPUs

["Ke, Liping" <liping.ke@xxxxxxxxx>]

Hi, All

According to Keir's suggestion, I re-organize those patches and make sure that 
each intermediate patch could be compiled and running.

Since remove old p4 and p6 files are hard to be split, I now put the remove and 
replace in the one patch. Is it ok?

Any comment, just let me know.
Thanks a lot for your help!
Criping

Following 3 patches are for enabling CMCI of Intel CPUs in XEN.
---------------------------------------------------------------------------
Patch 1: change_stop_machine_run.patch changes stopmachine_run interface so 
that we can designate the callback function running on the cpu_map instead of 
single one. We do this change because *cmci owner change* callback (please 
refer to note 3 below) needs to be executed on each of online cpus when do CPU 
hotplug. And also, we add a callback function for CMCI use before taking CPU 
down.
Patch 2: apic_cmci.patch adds the new CMCI LVT entry. And also it did small 
clean up jobs for thermal since thermal is not only P4 specific, but also later 
Intel CPUs common features. The old thermal removal will also be finished in 
patch 3 combined with old P4/p6 removals.
Patch 3: clean_and_cmci.patch contains the main CMCI support logic including 
removing old duplicated P4/P6 files, add new MCA/CMCI common init/interrupt 
processing, *CMCI owner judge algorithms* when (bring up CPUs or do CPU 
hotplug), polling mechanism, etc.
----------------------------------------------------------------------------
About Test 
We wrote CMCI injection tool to test the patch. Also we wrote DOM0 test patches 
to see whether logs are accepted by DOM0.
We test the patches on both CMCI-support and NO-CMCI-support machine.
We test the patches combined with CPU online/offline ops and S3&S5 ops which 
cause banks owner changing
----------------------------------------------------------------------------
Below notes might be helpful
1) CMCI use another apic_lvt entry (now max_lvt could be 6 in newer Intel 
platform)

2) CMCI is combined with polling mechanism since some CPUs don't support CMCI. 
And for supporting CPUs, still some banks don't support CMCI. So we keep 
polling mechanism. Also add simple policy, when find errors, shorten polling 
interval. Otherwise, lengthen intervals. 

3) MCA banks shares between cores/threads. For avoiding mis-ops, we need to 
judge *owner* for each bank. Each bank only has one owner, the owner manages 
the bank. The owner will be set up when cpu_up. Owners might be changed when 
doing cpu-hotplug.

4) When one CMCI interrupt is accepted and logged by XEN, XEN will notify DOM0. 
We don't plan to check in DOM0 code now.

For more info, please refer to latest Intel software development manual, 
Chapter 14.
--------------------------------------------------------------------------
Machine check (Uncorrectable Error) support will be sent in later patches, so 
we keep old machine check handling code. 

Any comment, just let us know. 
Thanks a lot for your help!
Regards,
Criping


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