Re: [Xen-devel] NPT and EPT question

["bo ma" <kyle.ma83@xxxxxxxxx>]

thank you ,Tim and Huang

2008/11/18 Wei Huang <wei.huang2@xxxxxxx>

I think Tim is right. On my spec (24593, Dec 2005), it is explained as the following:

"Table walks for guest page tables are always treated as user writes at the host level. For this reason,
* the page must be writable by user at the host level, or else a #VMEXIT(NPF) is raised, and
* the dirty and accessed bits are always set in the host page table entries that were touched during nested page table walks for guest page table entries"

As explained in the second one, CPU needs to update guest table entries (A and D bits, especially A bit) when it walks through guest table. That is why the dirty and accessed bits are set in host table.

-Wei

Tim Deegan wrote:

Hi,

At 21:23 +0800 on 17 Nov (1226957017), bo ma wrote:

Recent I read AMD specification about NPT,and met with a question about a
sentence.

The sentence is : Note that host table walks for guest page tables are
always treated as data writes.I don't know why treated as data writes?

Possibly because the guest-table walker might have to set the A and D
bits, and the hardware doesn't know whether it will do that until
_after_ it's done the host-table walk.

Maybe someone from AMD can clarify.

In intel EPT ,is it the same? or treated as data reads?

My impression is that EPT only requires write permissions if it actually
writes back an A or D bit, but I'm not sure.   It should be easy to check.

Cheers,

Tim

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