RE: [Xen-devel] RE: [patch][vtd] Remove ASSERT in hvmloader.c whenassigning disk controller to a guest

["Zhang, Li" <li.zhang@xxxxxxxxx>]

The registers exist in all *Intel* chipsets that we care about. And the
registers of some other vendors are different. Here we should add the
ASSERT vendor_id == 0x8086.
See the patch. Thanks.

>  -----Original Message-----
>  From: Keir Fraser [mailto:keir.fraser@xxxxxxxxxxxxx]
>  Sent: Wednesday, June 25, 2008 10:47 PM
>  To: Zhang, Li; xen-devel@xxxxxxxxxxxxxxxxxxx
>  Subject: Re: [Xen-devel] RE: [patch][vtd] Remove ASSERT in
hvmloader.c
>  whenassigning disk controller to a guest
>  
>  On 25/6/08 15:38, "Zhang, Li" <li.zhang@xxxxxxxxx> wrote:
>  
>  >>  If the device is not PIIX3 IDE, we also should do the two
>  > pci_writew().
>  >>  The 0x40 and 0x42 are timing registers of IDE0 and IDE1, and they
are
>  >>  used to enable the IDE command decoding function.
>  >>  And from the PIIX3, ICH to ICH10, the IDE timing registers
addresses
>  > are
>  >>  the same. So I think removing the ASSERT is OK. The original
comment
>  > in
>  >>  the file is a little puzzling.
>  
>  So the registers exist in all *Intel* chipsets that we care about.
What
>  about other vendors? Should we make the pci_writew() invocations
conditional
>  on vendor_id==0x8086?
>  
>   -- Keir
>

Attachment: hvmloader.patch
Description: hvmloader.patch

_______________________________________________
Xen-devel mailing list
Xen-devel@xxxxxxxxxxxxxxxxxxx
http://lists.xensource.com/xen-devel