Re: [Xen-devel] Question about implementation of 32-bit guests on64-bit hypervisor (IDT-related)

[Keir Fraser <Keir.Fraser@xxxxxxxxxxxx>]

On 7/12/07 20:47, "Vessey, Bruce A" <Bruce.Vessey@xxxxxxxxxx> wrote:

> We have some confusion regarding the assignment of hardware physical
> addresses to the HVMs.  If all 32-bit HVMs are run in legacy mode, then
> they would be restricted to using 32-bit PAE shadow page tables.  The
> maximum physical addressing of such tables is limited to 64GB, so this
> implies that all 32-bit HVMs must be located within the first 64GB of
> hardware physical memory.  However, your previous responses indicated
> that 32-bit HVMs do not have such a restriction.  So our conclusion is
> that 32-bit HVMs running in legacy mode using 32-bit PAE page tables are
> able to address hardware physical memory above the 64GB limit.  Is this
> correct?  Could we create two separate 32-bit HVM guests, assign each of
> them 64GB of memory, and have them run concurrently without any problems
> (assuming that the platform has sufficient memory installed)?

Yes. I believe that the Intel manuals are incorrect in stating that PAE
pagetables are restricted to 36-bit addressing. Processors which support
long mode have their physical address size advertised in CPUID, and I'm
pretty sure that addresses up to that size can be poked into 8-byte
pagetable entries whether the pagetable format is 64-bit-mode or pae-mode.
AMD state explicitly in their manual that PAE pagetables can address up to
52 bits, just like 64-bit pagetables, and that this is the architectural
limit. Furthermore, you guys (Unisys) have done testing on big memory ES7000
systems (>128GB), and those are Intel boxes -- and I expect some of your
testing has been 32-bit HVM guests? Given we allocate larger addresses
first, this would confirm that Intel really does allow addresses >64GB in
PAE pagetables in practice.

 -- Keir



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