Re: [Xen-devel] Buffered IO for IO?

[Mats Petersson <mats@xxxxxxxxxxxxxxxxx>]

At 10:44 21/07/2007, Keir Fraser wrote:



> On 20/7/07 22:33, "Zulauf, John" <john.zulauf@xxxxxxxxx> wrote:
>
> > Has anyone experimented with adding Buffered IO support for "out"
> > instructions?  Currently, the buffered io pages is only used for mmio
> > writes (and then only to vga space).  It seems quite straight-forward to
> > add.
>
> Is it safe to buffer, and hence arbitrarily delay, any I/O port write?

That would depend on the actual port - some are OK to delay, others 
are not. E.g. OUT to the serial port FIFO would be OK to delay for a 
bit, but the next IN from the status register would require 
preceeding OUT's to be flushed (and processed) before the IN can be 
correctly assessed - as otherwise the serial port may look like it's 
got an infinite FIFO, and/or data has already been sent, which is 
likely to NOT be the case.
To be perfect, you'd need a separate set of rules for each type of 
device, but I think it can be simplified by a "OUTs must be processed 
before INs can be processed" - so a long stream of OUT instructions 
could be batched up, but as soon as an IN happens, the batched OUTs 
will need to be processed.
How much there is to gain from this would be relatively easy to asses 
by counting the number of OUT between each IN - I suspect that 
there's a few OUTs per IN, so there would be some gain to just return 
back to the guest after an OUT.
The real trouble, of course, comes if there are devices that use a 
mixture of IOIO and MMIO, where a IOIO is used to send data, and 
status is read from MMIO... This would complicate matters by adding a 
rule of "MMIO read must flush batched OUT". The only suspect device I 
can think of here is a IDE controller with DMA capabilities - I 
haven't looked at those, so I don't know if they mix IOIO and MMIO.
--
Mats


>  -- Keir
>
>
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