RE: [Xen-devel] [PATCH 3/10] Add HVM support

["Tian, Kevin" <kevin.tian@xxxxxxxxx>]

>From: Tian, Kevin
>Sent: 2007年7月10日 20:50
>
>>From: Keir Fraser [mailto:keir@xxxxxxxxxxxxx]
>>Sent: 2007年7月10日 17:51
>>
>>Kevin,
>>
>>Is it documented anywhere in which CPU states VMCS synchronisation
>>may be
>>lost? I see it makes sense that S3 would do so since the CPUs are
>>powered
>>off in that state (although I don't see this documented anywhere --
>maybe
>>it's 'obvious'), but what about e.g., Deep Sleep (C states)?
>
>I don't see either. Since S3 is triggered by I/O write to chipset, CPUs
>are immediately powered off as result and thus internal VMCS cache
>is also lost. All the CPU context favored by system software should
>be saved by system software before that I/O write. So I thought it as
>'obvious'. :-)
>
>For deep sleep states, IPI is taken as break event to bring that
>CPU back to working state (C0).

Seems that I misunderstood your question. Normally such information 
is described in ICH spec and I didn't see VMX related warn by far for 
deep C states. Some deep C state is described with implicit cache flush 
which, I assume, also applies to the internal VMCS cache too. Or else 
all the side effects will be explicitly described such as LAPIC timer stop 
in some deep state. In that case, software needs to tackle that effect 
correspondingly.

Thanks,
Kevin

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