[Date Prev][Date Next][Thread Prev][Thread Next][Date Index][Thread Index] Re: [Xen-devel] Vitrual TLBs
AMD will provide support for nested paging that caches address translations to reduce memory accesses in its latest quad-core CPUs. As the hypervisor can get pretty bogged down managing all of this and the processor is constantly switching from guest OS mode to hypervisor mode and back, Nesting page tables and caching memory addresses are ways of freeing things up as it cuts down on memory access time. So Xen may not need such kind of virtual TLB anymore. Liang----- Original Message ----- From: "Anthony Liguori" <aliguori@xxxxxxxxxx> To: "Sameer Ahuja" <sameer.ahuja@xxxxxxxxxxx>Cc: "Tim Deegan" <Tim.Deegan@xxxxxxxxxxxxx>; <sameer.ahuja81@xxxxxxxxx>; <xen-devel@xxxxxxxxxxxxxxxxxxx> Sent: Monday, November 20, 2006 9:53 AM Subject: Re: [Xen-devel] Vitrual TLBs Sameer Ahuja wrote:Hi, Does XEN have the concept of virtual TLBs?Not really. Regards, Anthony LiguoriRegards, Sameer _______________________________________________ Xen-devel mailing list Xen-devel@xxxxxxxxxxxxxxxxxxx http://lists.xensource.com/xen-devel_______________________________________________ Xen-devel mailing list Xen-devel@xxxxxxxxxxxxxxxxxxx http://lists.xensource.com/xen-devel _______________________________________________ Xen-devel mailing list Xen-devel@xxxxxxxxxxxxxxxxxxx http://lists.xensource.com/xen-devel
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