[xen master] xen/riscv: drop INSN_{16,32}BIT_MASK and report unknown instruction lengths

[patchbot@xxxxxxx]

commit 6c8e95db7c3f981dfee47618a23947c98e351cca
Author:     Oleksii Kurochko <oleksii.kurochko@xxxxxxxxx>
AuthorDate: Mon Oct 12 09:40:25 2026 +0200
Commit:     Jan Beulich <jbeulich@xxxxxxxx>
CommitDate: Mon Oct 12 09:40:25 2026 +0200

    xen/riscv: drop INSN_{16,32}BIT_MASK and report unknown instruction lengths
    
    Both constants were inherited from OpenSBI and their names are misleading.
    The length of an instruction is encoded in its low bits: bits[1:0] != 11
    means 16 bits, otherwise bits[4:2] != 111 means 32 bits, and anything else
    is 48 bits or wider. 0x3 and 0x1c are the patterns compared against in
    these two tests, not masks selecting a 16-bit or a 32-bit instruction. As
    each constant is needed in one place only, once INSN_IS_16BIT() and
    INSN_IS_32BIT() encapsulate the tests, drop them and spell the values out
    in those two macros instead.
    
    While at it, make INSN_LEN() cover the case both macros already knew about:
    an encoding of 48 bits or wider now yields 0 rather than being silently
    taken for a 32-bit instruction. No ratified extension defines an instruction
    of such a length, so rather than open-coding a decoder for encodings which
    cannot legitimately occur, leave it to the caller to treat the 0 as an
    illegal instruction.
    
    No functional change: the only present caller applies INSN_LEN() to a bug
    frame, i.e. to an instruction emitted by Xen itself, which is either 16 or
    32 bits wide.
    
    Suggested-by: Jan Beulich <jbeulich@xxxxxxxx>
    Signed-off-by: Oleksii Kurochko <oleksii.kurochko@xxxxxxxxx>
    Reviewed-by: Baptiste Le Duc <baptiste.le-duc@xxxxxxxxxx>
    Acked-by: Jan Beulich <jbeulich@xxxxxxxx>
---
 xen/arch/riscv/include/asm/riscv_encoding.h | 20 +++++++++++---------
 1 file changed, 11 insertions(+), 9 deletions(-)

diff --git a/xen/arch/riscv/include/asm/riscv_encoding.h 
b/xen/arch/riscv/include/asm/riscv_encoding.h
index 03e186bcdb..647268e6d0 100644
--- a/xen/arch/riscv/include/asm/riscv_encoding.h
+++ b/xen/arch/riscv/include/asm/riscv_encoding.h
@@ -857,16 +857,18 @@
 #error "Unexpected __riscv_xlen"
 #endif
 
-#define INSN_16BIT_MASK                        0x3
-#define INSN_32BIT_MASK                        0x1c
+#define INSN_IS_16BIT(insn)    (((insn) & 3) != 3)
+#define INSN_IS_32BIT(insn)    (!INSN_IS_16BIT(insn) && ((insn) & 0x1c) != 
0x1c)
 
-#define INSN_IS_16BIT(insn)            \
-       (((insn) & INSN_16BIT_MASK) != INSN_16BIT_MASK)
-#define INSN_IS_32BIT(insn)            \
-       (((insn) & INSN_16BIT_MASK) == INSN_16BIT_MASK && \
-        ((insn) & INSN_32BIT_MASK) != INSN_32BIT_MASK)
-
-#define INSN_LEN(insn)                 (INSN_IS_16BIT(insn) ? 2 : 4)
+/*
+ * Length in bytes of the instruction whose first parcel is @insn: 2 or 4, or
+ * 0 when the encoding is 48 bits or wider. No ratified extension defines an
+ * instruction of such a length, so rather than open-coding a decoder for
+ * encodings which cannot legitimately occur, leave it to the caller to treat
+ * the 0 as an illegal instruction.
+ */
+#define INSN_LEN(insn) \
+       (INSN_IS_16BIT(insn) ? 2 : (INSN_IS_32BIT(insn) ? 4 : 0))
 
 #if __riscv_xlen == 64
 #define LOG_REGBYTES                   3
--
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