[xen staging] xen/riscv: use ~0 instead of ULONG_MAX to disable the VS-timer

[patchbot@xxxxxxx]

commit a92d2ba89bf8936389c75b8d3ff8d0c71073ce79
Author:     Oleksii Kurochko <oleksii.kurochko@xxxxxxxxx>
AuthorDate: Mon Oct 12 09:41:31 2026 +0200
Commit:     Jan Beulich <jbeulich@xxxxxxxx>
CommitDate: Mon Oct 12 09:41:31 2026 +0200

    xen/riscv: use ~0 instead of ULONG_MAX to disable the VS-timer
    
    vstimecmp is a 64-bit CSR independently of XLEN, which is why it is
    written with csr_write64(). On RV32 that macro splits the value into
    the vstimecmp/vstimecmph pair, so passing ULONG_MAX (0xffffffff there)
    writes all ones to the low half and zero to the high half, leaving the
    CSR at 0x00000000ffffffff rather than at its maximum. A VS-timer irq
    would then become pending as soon as (time + htimedelta) reaches 2^32,
    which is exactly what the code is trying to avoid.
    
    Use ~0 instead: csr_write64() converts its argument to uint64_t, and the
    conversion of the signed -1 sign-extends to all ones, so both halves get
    0xffffffff. On RV64 the result is equal to ULONG_MAX, so no functional
    change there.
    
    Fixes: 25e032730690 ("xen/riscv: allow Xen to use SSTC while hiding it from 
guests")
    Signed-off-by: Oleksii Kurochko <oleksii.kurochko@xxxxxxxxx>
    Reviewed-by: Baptiste Le Duc <baptiste.le-duc@xxxxxxxxxx>
    Acked-by: Jan Beulich <jbeulich@xxxxxxxx>
---
 xen/arch/riscv/time.c | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/xen/arch/riscv/time.c b/xen/arch/riscv/time.c
index 602c029641..782d9cd450 100644
--- a/xen/arch/riscv/time.c
+++ b/xen/arch/riscv/time.c
@@ -101,8 +101,8 @@ void __init preinit_xen_time(void)
          * A VS-timer interrupt becomes pending whenever the value of
          * (time + htimedelta) is greater than or equal to vstimecmp CSR.
          * Thereby to avoid spurious VS-timer irqs set vstimecmp CSR to
-         * ULONG_MAX.
+         * ~0.
          */
-        csr_write64(CSR_VSTIMECMP, ULONG_MAX);
+        csr_write64(CSR_VSTIMECMP, ~0);
     }
 }
--
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