[xen staging-4.20] xen/arm: drop incorrect EL0 accessibility comments for PMINTEN{SET,CLR}

[patchbot@xxxxxxx]

commit 1633c8148acbf9fccfbd06a9aaaa16f71b7856b2
Author:     Michal Orzel <michal.orzel@xxxxxxx>
AuthorDate: Tue Aug 11 15:08:18 2026 +0200
Commit:     Michal Orzel <michal.orzel@xxxxxxx>
CommitDate: Mon Sep 21 14:04:44 2026 +0200

    xen/arm: drop incorrect EL0 accessibility comments for PMINTEN{SET,CLR}
    
    The comments on the PMINTENSET/PMINTENCLR cases claim that an EL0 access
    may be trapped to EL2 when MDCR_EL2.TPM is set, and that such a case is
    handled. Both are inaccurate. PMINTENSET_EL1/PMINTENCLR_EL1 are accessible
    at EL1 and above only, with no enable making them accessible at EL0.
    
    Arm ARM (DDI 0487M.b) D1.4.5.6 "Prioritization of Synchronous
    exceptions" orders the two exceptions. An access that is never
    accessible at the current Exception level regardless of any enables or
    traps is priority 18, whereas an exception taken to EL2 as the result of
    a configuration control in MDCR_EL2 is priority 24. An EL0 access is
    therefore UNDEFINED and taken to EL1.
    
    Signed-off-by: Michal Orzel <michal.orzel@xxxxxxx>
    Reviewed-by: Stefano Stabellini <sstabellini@xxxxxxxxxx>
    (cherry picked from commit 87a8a5728e5936f088c94bd7960c70f9b1cef36e)
---
 xen/arch/arm/arm64/vsysreg.c | 4 ----
 xen/arch/arm/vcpreg.c        | 1 -
 2 files changed, 5 deletions(-)

diff --git a/xen/arch/arm/arm64/vsysreg.c b/xen/arch/arm/arm64/vsysreg.c
index c73b2c95ce..207c868059 100644
--- a/xen/arch/arm/arm64/vsysreg.c
+++ b/xen/arch/arm/arm64/vsysreg.c
@@ -229,10 +229,6 @@ void do_sysreg(struct cpu_user_regs *regs,
      */
     case HSR_SYSREG_PMINTENSET_EL1:
     case HSR_SYSREG_PMINTENCLR_EL1:
-        /*
-         * Accessible from EL1 only, but if EL0 trap happens handle as
-         * undef.
-         */
         return handle_raz_wi(regs, regidx, hsr.sysreg.read, hsr, 1);
     case HSR_SYSREG_PMUSERENR_EL0:
         /* RO at EL0. RAZ/WI at EL1 */
diff --git a/xen/arch/arm/vcpreg.c b/xen/arch/arm/vcpreg.c
index 0b336875a4..2ed27084c1 100644
--- a/xen/arch/arm/vcpreg.c
+++ b/xen/arch/arm/vcpreg.c
@@ -294,7 +294,6 @@ void do_cp15_32(struct cpu_user_regs *regs, const union hsr 
hsr)
             return handle_raz_wi(regs, regidx, cp32.read, hsr, 1);
     case HSR_CPREG32(PMINTENSET):
     case HSR_CPREG32(PMINTENCLR):
-        /* EL1 only, however MDCR_EL2.TPM==1 means EL0 may trap here also. */
         return handle_raz_wi(regs, regidx, cp32.read, hsr, 1);
     case HSR_CPREG32(PMCR):
     case HSR_CPREG32(PMCNTENSET):
--
generated by git-patchbot for /home/xen/git/xen.git#staging-4.20