[xen stable-4.21] xen/arm: Sync missing definitions for Arm CPUs with Linux

[patchbot@xxxxxxx]

commit 8851d2e1089e0df6ee289cc1b18ef5e25739bbcb
Author:     Michal Orzel <michal.orzel@xxxxxxx>
AuthorDate: Fri May 22 09:35:55 2026 +0200
Commit:     Andrew Cooper <andrew.cooper3@xxxxxxxxxx>
CommitDate: Thu Jun 4 21:38:04 2026 +0100

    xen/arm: Sync missing definitions for Arm CPUs with Linux
    
    Synchronize with Linux kernel 7.0 definitions for the following CPUs:
     - Cortex-A76AE,
     - Cortex-A78AE,
     - Cortex-X1C,
     - Cortex-X3,
     - Neoverse-V2,
     - Cortex-X4,
     - Neoverse-V3AE,
     - Neoverse-V3,
     - Cortex-X925.
    
    These will be used for errata detection in subsequent patches.
    
    Signed-off-by: Michal Orzel <michal.orzel@xxxxxxx>
    Reviewed-by: Julien Grall <julien@xxxxxxx>
    (cherry picked from commit d54682a5b23d7a22a0f1aa74130bd1ed8a669db1)
---
 xen/arch/arm/include/asm/processor.h | 18 ++++++++++++++++++
 1 file changed, 18 insertions(+)

diff --git a/xen/arch/arm/include/asm/processor.h 
b/xen/arch/arm/include/asm/processor.h
index ec23fd098b..907778683b 100644
--- a/xen/arch/arm/include/asm/processor.h
+++ b/xen/arch/arm/include/asm/processor.h
@@ -89,13 +89,22 @@
 #define ARM_CPU_PART_CORTEX_A76     0xD0B
 #define ARM_CPU_PART_NEOVERSE_N1    0xD0C
 #define ARM_CPU_PART_CORTEX_A77     0xD0D
+#define ARM_CPU_PART_CORTEX_A76AE   0xD0E
 #define ARM_CPU_PART_NEOVERSE_V1    0xD40
 #define ARM_CPU_PART_CORTEX_A78     0xD41
+#define ARM_CPU_PART_CORTEX_A78AE   0xD42
 #define ARM_CPU_PART_CORTEX_X1      0xD44
 #define ARM_CPU_PART_CORTEX_A710    0xD47
 #define ARM_CPU_PART_CORTEX_X2      0xD48
 #define ARM_CPU_PART_NEOVERSE_N2    0xD49
 #define ARM_CPU_PART_CORTEX_A78C    0xD4B
+#define ARM_CPU_PART_CORTEX_X1C     0xD4C
+#define ARM_CPU_PART_CORTEX_X3      0xD4E
+#define ARM_CPU_PART_NEOVERSE_V2    0xD4F
+#define ARM_CPU_PART_CORTEX_X4      0xD82
+#define ARM_CPU_PART_NEOVERSE_V3AE  0xD83
+#define ARM_CPU_PART_NEOVERSE_V3    0xD84
+#define ARM_CPU_PART_CORTEX_X925    0xD85
 
 #define MIDR_CORTEX_A12 MIDR_CPU_MODEL(ARM_CPU_IMP_ARM, 
ARM_CPU_PART_CORTEX_A12)
 #define MIDR_CORTEX_A17 MIDR_CPU_MODEL(ARM_CPU_IMP_ARM, 
ARM_CPU_PART_CORTEX_A17)
@@ -110,13 +119,22 @@
 #define MIDR_CORTEX_A76 MIDR_CPU_MODEL(ARM_CPU_IMP_ARM, 
ARM_CPU_PART_CORTEX_A76)
 #define MIDR_NEOVERSE_N1 MIDR_CPU_MODEL(ARM_CPU_IMP_ARM, 
ARM_CPU_PART_NEOVERSE_N1)
 #define MIDR_CORTEX_A77 MIDR_CPU_MODEL(ARM_CPU_IMP_ARM, 
ARM_CPU_PART_CORTEX_A77)
+#define MIDR_CORTEX_A76AE MIDR_CPU_MODEL(ARM_CPU_IMP_ARM, 
ARM_CPU_PART_CORTEX_A76AE)
 #define MIDR_NEOVERSE_V1 MIDR_CPU_MODEL(ARM_CPU_IMP_ARM, 
ARM_CPU_PART_NEOVERSE_V1)
 #define MIDR_CORTEX_A78 MIDR_CPU_MODEL(ARM_CPU_IMP_ARM, 
ARM_CPU_PART_CORTEX_A78)
+#define MIDR_CORTEX_A78AE MIDR_CPU_MODEL(ARM_CPU_IMP_ARM, 
ARM_CPU_PART_CORTEX_A78AE)
 #define MIDR_CORTEX_X1  MIDR_CPU_MODEL(ARM_CPU_IMP_ARM, ARM_CPU_PART_CORTEX_X1)
 #define MIDR_CORTEX_A710 MIDR_CPU_MODEL(ARM_CPU_IMP_ARM, 
ARM_CPU_PART_CORTEX_A710)
 #define MIDR_CORTEX_X2  MIDR_CPU_MODEL(ARM_CPU_IMP_ARM, ARM_CPU_PART_CORTEX_X2)
 #define MIDR_NEOVERSE_N2 MIDR_CPU_MODEL(ARM_CPU_IMP_ARM, 
ARM_CPU_PART_NEOVERSE_N2)
 #define MIDR_CORTEX_A78C MIDR_CPU_MODEL(ARM_CPU_IMP_ARM, 
ARM_CPU_PART_CORTEX_A78C)
+#define MIDR_CORTEX_X1C MIDR_CPU_MODEL(ARM_CPU_IMP_ARM, 
ARM_CPU_PART_CORTEX_X1C)
+#define MIDR_CORTEX_X3 MIDR_CPU_MODEL(ARM_CPU_IMP_ARM, ARM_CPU_PART_CORTEX_X3)
+#define MIDR_NEOVERSE_V2 MIDR_CPU_MODEL(ARM_CPU_IMP_ARM, 
ARM_CPU_PART_NEOVERSE_V2)
+#define MIDR_CORTEX_X4 MIDR_CPU_MODEL(ARM_CPU_IMP_ARM, ARM_CPU_PART_CORTEX_X4)
+#define MIDR_NEOVERSE_V3AE MIDR_CPU_MODEL(ARM_CPU_IMP_ARM, 
ARM_CPU_PART_NEOVERSE_V3AE)
+#define MIDR_NEOVERSE_V3 MIDR_CPU_MODEL(ARM_CPU_IMP_ARM, 
ARM_CPU_PART_NEOVERSE_V3)
+#define MIDR_CORTEX_X925 MIDR_CPU_MODEL(ARM_CPU_IMP_ARM, 
ARM_CPU_PART_CORTEX_X925)
 
 /* MPIDR Multiprocessor Affinity Register */
 #define _MPIDR_UP           (30)
--
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