[xen staging] xen/arm: gic-v3: disable Group 1 before CPU power-down

[patchbot@xxxxxxx]

commit 18b718b6af3d38d8bed23439ec396fd4bde9b75d
Author:     Mykola Kvach <mykola_kvach@xxxxxxxx>
AuthorDate: Fri Apr 10 09:47:45 2026 +0200
Commit:     Michal Orzel <michal.orzel@xxxxxxx>
CommitDate: Fri Apr 10 12:14:05 2026 +0200

    xen/arm: gic-v3: disable Group 1 before CPU power-down
    
    gicv3_cpu_disable() currently writes 0 to ICC_CTLR_EL1. Unlike
    GICC_CTLR in the GICv2 path, ICC_CTLR_EL1 does not enable or disable
    physical Group 1 interrupt signalling, so this write only clears
    EOImode.
    
    The GICv3 power management rules require the physical group enables in
    the CPU interface to be cleared before the redistributor is driven into
    ProcessorSleep, otherwise behaviour is UNPREDICTABLE. Xen only enables
    Group 1 interrupts on this path, so disable the interface by clearing
    ICC_IGRPEN1_EL1 instead.
    
    This appears to be a copy of the GICv2 pattern where the enable control
    lives in CTLR, but for GICv3 the enable moved to ICC_IGRPEN1_EL1.
    
    Fixes: bc183a0235e ("xen/arm: Add support for GIC v3")
    Signed-off-by: Mykola Kvach <mykola_kvach@xxxxxxxx>
    Reviewed-by: Michal Orzel <michal.orzel@xxxxxxx>
---
 xen/arch/arm/gic-v3.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/xen/arch/arm/gic-v3.c b/xen/arch/arm/gic-v3.c
index 5641ee870f..7f365cdbe9 100644
--- a/xen/arch/arm/gic-v3.c
+++ b/xen/arch/arm/gic-v3.c
@@ -1028,7 +1028,7 @@ static int gicv3_cpu_init(void)
 
 static void gicv3_cpu_disable(void)
 {
-    WRITE_SYSREG(0, ICC_CTLR_EL1);
+    WRITE_SYSREG(0, ICC_IGRPEN1_EL1);
     isb();
 }
 
--
generated by git-patchbot for /home/xen/git/xen.git#staging