[xen staging] x86/cpu/intel: Limit the non-architectural constant_tsc model checks

[patchbot@xxxxxxx]

commit 0acaba1257651e531ea79be789d0671d9c56b169
Author:     Sohil Mehta <sohil.mehta@xxxxxxxxx>
AuthorDate: Wed Feb 19 18:41:31 2025 +0000
Commit:     Andrew Cooper <andrew.cooper3@xxxxxxxxxx>
CommitDate: Fri Feb 20 10:37:42 2026 +0000

    x86/cpu/intel: Limit the non-architectural constant_tsc model checks
    
    X86_FEATURE_CONSTANT_TSC is a Linux-defined, synthesized feature flag.
    It is used across several vendors. Intel CPUs will set the feature when
    the architectural CPUID.80000007.EDX[1] bit is set. There are also some
    Intel CPUs that have the X86_FEATURE_CONSTANT_TSC behavior but don't
    enumerate it with the architectural bit.  Those currently have a model
    range check.
    
    Today, virtually all of the CPUs that have the CPUID bit *also* match
    the "model >= 0x0e" check. This is confusing. Instead of an open-ended
    check, pick some models (INTEL_IVYBRIDGE and P4_WILLAMETTE) as the end
    of goofy CPUs that should enumerate the bit but don't.  These models are
    relatively arbitrary but conservative pick for this.
    
    This makes it obvious that later CPUs (like Family 18+) no longer need
    to synthesize X86_FEATURE_CONSTANT_TSC.
    
    Signed-off-by: Sohil Mehta <sohil.mehta@xxxxxxxxx>
    Signed-off-by: Ingo Molnar <mingo@xxxxxxxxxx>
    Link: 
https://lore.kernel.org/r/20250219184133.816753-14-sohil.mehta@xxxxxxxxx
    Link: https://git.kernel.org/tip/fadb6f569b10bf668677add876ed50586931b8f3
    [Port to Xen]
    Signed-off-by: Kevin Lampis <kevin.lampis@xxxxxxxxxx>
    Signed-off-by: Andrew Cooper <andrew.cooper3@xxxxxxxxxx>
---
 xen/arch/x86/cpu/intel.c | 7 +++----
 1 file changed, 3 insertions(+), 4 deletions(-)

diff --git a/xen/arch/x86/cpu/intel.c b/xen/arch/x86/cpu/intel.c
index 584588e406..18b3c79dc9 100644
--- a/xen/arch/x86/cpu/intel.c
+++ b/xen/arch/x86/cpu/intel.c
@@ -637,14 +637,13 @@ static void cf_check init_intel(struct cpuinfo_x86 *c)
        /* Work around errata */
        Intel_errata_workarounds(c);
 
-       if ((c->x86 == 0xf && c->x86_model >= 0x03) ||
-               (c->x86 == 0x6 && c->x86_model >= 0x0e))
-               __set_bit(X86_FEATURE_CONSTANT_TSC, c->x86_capability);
        if (cpu_has(c, X86_FEATURE_ITSC)) {
                __set_bit(X86_FEATURE_CONSTANT_TSC, c->x86_capability);
                __set_bit(X86_FEATURE_NONSTOP_TSC, c->x86_capability);
                __set_bit(X86_FEATURE_TSC_RELIABLE, c->x86_capability);
-       }
+       } else if ((c->vfm >= INTEL_P4_PRESCOTT && c->vfm <= 
INTEL_P4_CEDARMILL) ||
+                  (c->vfm >= INTEL_CORE_YONAH && c->vfm <= INTEL_IVYBRIDGE))
+               __set_bit(X86_FEATURE_CONSTANT_TSC, c->x86_capability);
 
        if ((opt_cpu_info && !(c->apicid & (c->x86_num_siblings - 1))) ||
            c == &boot_cpu_data )
--
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