[xen master] xen/riscv: avoid reading hstateen0 when Smstateen is not implemented

[patchbot@xxxxxxx]

commit e1689365dad3feda6400addd7396896796908e5d
Author:     Oleksii Kurochko <oleksii.kurochko@xxxxxxxxx>
AuthorDate: Wed Feb 11 09:20:51 2026 +0100
Commit:     Jan Beulich <jbeulich@xxxxxxxx>
CommitDate: Wed Feb 11 09:20:51 2026 +0100

    xen/riscv: avoid reading hstateen0 when Smstateen is not implemented
    
    If the Smstateen extension is not implemented, the hstateen0 CSR is
    considered non-existent. Any attempt to access it will raise an
    illegal-instruction exception.
    
    Guard the hstateen0 dump with a runtime check for Smstateen support to
    avoid triggering traps when dumping CSRs on systems that do not
    implement this extension.
    
    Fixes: 3babc8d2e546 ("xen/riscv: dump GPRs and CSRs on unexpected traps")
    Signed-off-by: Oleksii Kurochko <oleksii.kurochko@xxxxxxxxx>
    Reviewed-by: Jan Beulich <jbeulich@xxxxxxxx>
---
 xen/arch/riscv/cpufeature.c             | 1 +
 xen/arch/riscv/include/asm/cpufeature.h | 1 +
 xen/arch/riscv/traps.c                  | 8 +++++++-
 3 files changed, 9 insertions(+), 1 deletion(-)

diff --git a/xen/arch/riscv/cpufeature.c b/xen/arch/riscv/cpufeature.c
index 02b68aeaa4..03e27b037b 100644
--- a/xen/arch/riscv/cpufeature.c
+++ b/xen/arch/riscv/cpufeature.c
@@ -137,6 +137,7 @@ const struct riscv_isa_ext_data __initconst riscv_isa_ext[] 
= {
     RISCV_ISA_EXT_DATA(zbb),
     RISCV_ISA_EXT_DATA(zbs),
     RISCV_ISA_EXT_DATA(smaia),
+    RISCV_ISA_EXT_DATA(smstateen),
     RISCV_ISA_EXT_DATA(ssaia),
     RISCV_ISA_EXT_DATA(svade),
     RISCV_ISA_EXT_DATA(svpbmt),
diff --git a/xen/arch/riscv/include/asm/cpufeature.h 
b/xen/arch/riscv/include/asm/cpufeature.h
index b696160388..ef02a3e26d 100644
--- a/xen/arch/riscv/include/asm/cpufeature.h
+++ b/xen/arch/riscv/include/asm/cpufeature.h
@@ -36,6 +36,7 @@ enum riscv_isa_ext_id {
     RISCV_ISA_EXT_zbb,
     RISCV_ISA_EXT_zbs,
     RISCV_ISA_EXT_smaia,
+    RISCV_ISA_EXT_smstateen,
     RISCV_ISA_EXT_ssaia,
     RISCV_ISA_EXT_svade,
     RISCV_ISA_EXT_svpbmt,
diff --git a/xen/arch/riscv/traps.c b/xen/arch/riscv/traps.c
index 34920f4e56..c81a4f79a0 100644
--- a/xen/arch/riscv/traps.c
+++ b/xen/arch/riscv/traps.c
@@ -11,6 +11,7 @@
 #include <xen/nospec.h>
 #include <xen/sched.h>
 
+#include <asm/cpufeature.h>
 #include <asm/intc.h>
 #include <asm/processor.h>
 #include <asm/riscv_encoding.h>
@@ -144,7 +145,12 @@ static void dump_csrs(const char *ctx)
       (v & HSTATUS_SPV)  ? " SPV"  : "",
       (v & HSTATUS_GVA)  ? " GVA"  : "");
     X(hgatp, CSR_HGATP, "\n");
-    X(hstateen0, CSR_HSTATEEN0, "\n");
+
+    if ( riscv_isa_extension_available(NULL, RISCV_ISA_EXT_smstateen) )
+    {
+        X(hstateen0, CSR_HSTATEEN0, "\n");
+    }
+
     X(stvec, CSR_STVEC, " "); X(vstvec, CSR_VSTVEC, "\n");
     X(sepc, CSR_SEPC, " "); X(vsepc, CSR_VSEPC, "\n");
     X(stval, CSR_STVAL, " "); X(vstval, CSR_VSTVAL, "\n");
--
generated by git-patchbot for /home/xen/git/xen.git#master