[xen master] arm: Use secure hypervisor timer in MPU system

[patchbot@xxxxxxx]

commit e232aa054ce197a6d9cc54796d09ba42a9b377ed
Author:     Penny Zheng <Penny.Zheng@xxxxxxx>
AuthorDate: Wed Jan 14 14:27:33 2026 +0000
Commit:     Michal Orzel <michal.orzel@xxxxxxx>
CommitDate: Fri Jan 16 09:38:30 2026 +0100

    arm: Use secure hypervisor timer in MPU system
    
    As MPU systems only have one secure state, we have to use secure EL2
    hypervisor timer for Xen in secure EL2.
    
    Signed-off-by: Penny Zheng <penny.zheng@xxxxxxx>
    Signed-off-by: Wei Chen <wei.chen@xxxxxxx>
    Signed-off-by: Luca Fancellu <luca.fancellu@xxxxxxx>
    Signed-off-by: Harry Ramsey <harry.ramsey@xxxxxxx>
    Reviewed-by: Ayan Kumar Halder <ayan.kumar.halder@xxxxxxx>
    Acked-by: Michal Orzel <michal.orzel@xxxxxxx>
---
 xen/arch/arm/include/asm/arm64/sysregs.h | 11 +++++++++++
 1 file changed, 11 insertions(+)

diff --git a/xen/arch/arm/include/asm/arm64/sysregs.h 
b/xen/arch/arm/include/asm/arm64/sysregs.h
index 7dfd20414d..19d409d3eb 100644
--- a/xen/arch/arm/include/asm/arm64/sysregs.h
+++ b/xen/arch/arm/include/asm/arm64/sysregs.h
@@ -462,6 +462,17 @@
 #define ZCR_ELx_LEN_SIZE             9
 #define ZCR_ELx_LEN_MASK             0x1ff
 
+#ifdef CONFIG_MPU
+/*
+ * The Armv8-R AArch64 architecture always executes code in Secure
+ * state with EL2 as the highest exception level.
+ *
+ * Hypervisor timer registers for Secure EL2.
+ */
+#define CNTHP_CTL_EL2   CNTHPS_CTL_EL2
+#define CNTHP_CVAL_EL2  CNTHPS_CVAL_EL2
+#endif
+
 #define REGION_TEXT_PRBAR       0x38    /* SH=11 AP=10 XN=00 */
 #define REGION_RO_PRBAR         0x3A    /* SH=11 AP=10 XN=10 */
 #define REGION_DATA_PRBAR       0x32    /* SH=11 AP=00 XN=10 */
--
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